Interconnect levels with multiple line types
A semiconductor structure with a first backside metal level that has a plurality of first type of lines and at least one second type line. The first type of lines have a wider top surface than the bottom surface and have a first width. The first type of lines each connect by a first via to a second backside metal level. Each of first type of lines and the second type line connect by a second via to a through-silicon via. The second type line is narrower than the first type of lines. Each of the second type line is between adjacent first type of lines. The second type line has a top surface that is in the middle of the first type of lines, below the first type of lines, above, or level with the top surface of the first type of lines.
1 . A semiconductor structure comprising:
a plurality of first type of lines in a first metal level with a first line width and a first height, wherein each line of the plurality of first type of lines has a top surface wider than a bottom surface; and
a second type of line in the first metal level with a second line width that is narrower than the first line width in the first metal level, wherein:
a single line of the second type of line is an only line separating adjacent first type of lines;
the second type line has a top surface wider than a bottom surface; and
the top surface of the second type of line is on a plane offset from each of the top surfaces of the plurality of first type of lines.
2 . The semiconductor structure of claim 1 , further comprising:
a plurality of first vias, wherein each of the plurality of first vias connects a line selected from the group consisting of: (i) the plurality of first type of lines and (ii) the second type line, to a second backside metal level, wherein the first metal level is a first backside metal level.
3 . The semiconductor structure of claim 2 , wherein each of the plurality of first type of lines and the second type of line connect by a via of a plurality of second vias to a through-silicon via of a plurality of through-silicon vias.
4 . The semiconductor structure of claim 2 , further comprising:
a third backside metal level includes a plurality of second backside first type of lines and second backside second type of line, wherein the second backside second type of line is between two adjacent lines of the plurality of second backside first type of lines; and
a plurality of third vias connecting: (i) the plurality of second backside first type of lines and (ii) the second backside second type of line, to the second backside metal level.
5 . The semiconductor structure of claim 2 , wherein:
the top surface of the second type of line is above the top surface of the plurality of first type lines; and
the second type of line has a same height as the first height of the plurality of first type of lines.
6 . The semiconductor structure of claim 2 , wherein:
the top surface of the second type of line is level with a bottom surface of the plurality of first type of lines; and
the second type of line is composed of a different metal material than the plurality of first type of lines.
7 . The semiconductor structure of claim 2 , wherein:
the top surface of the second type of line is level with a bottom surface of the plurality of first type of lines; and
the second type of line has a height that is less than the first height.
8 . The semiconductor structure of claim 2 , wherein the top surface of the second type of line is below a top surface of the plurality of first type of lines and above a bottom surface of the plurality of first type of lines.
9 . The semiconductor structure of claim 2 , wherein:
the first backside metal level includes more than one second type of line; and
each of the more than one second type of line has a different height.
10 . The semiconductor structure of claim 2 , wherein each of the plurality of first type of lines and the second type of line connect by a via of a plurality of second vias to a metal level that is closer to a backside of a semiconductor substrate than the first backside metal level.
11 . A semiconductor structure comprising:
a plurality of first type of lines with a first line width in a first backside metal level, wherein each of the plurality of first type of lines have a top surface wider than a bottom surface; and
a second type of line in the first backside metal level with a second line width that is less than the first line width, wherein:
each of the second type of line is between adjacent first type of lines;
a single line of the second type of line is an only line separating two adjacent first type of lines; and
the single line of the second type of line has a top surface on a plane offset from each of the top surfaces of the plurality of first type of lines.
12 . The semiconductor structure of claim 11 , further comprising:
a plurality of first vias connecting each of the plurality of first type of lines and the second type of line to one of a plurality of through-silicon vias, wherein the second type line with the wider top surface than the line bottom surface has a different height than the plurality of first type of lines; and
a plurality of second vias connecting each of the plurality of first type of lines and the second type of line to a second backside metal level.
13 . The semiconductor structure of claim 11 , further comprising:
a plurality of first vias connecting each of the plurality of first type of lines and the second type of line to a second metal level closer to a backside of a semiconductor substrate than the first metal level; and
a plurality of second vias connecting each of the plurality of first type of lines and the second type of line to a third backside metal level under the first backside metal level, wherein the second type of line has a top surface that is below a top surface of the plurality of first type of lines.
14 . A semiconductor structure comprising:
a plurality of first type of lines with a first line width in a first front side metal level, wherein each of the plurality of first type of lines have a wider top surface than a bottom surface;
a second type of line with a second line width that is wider than the first line width, wherein each of the second type of line is between adjacent first type of lines; and
a plurality of first vias connecting: (i) each of the plurality of first type of lines and (ii) the second type of line, to a second front side metal level.
15 . The semiconductor structure of claim 14 , wherein:
the second type of line is shorter than the plurality of first type of lines; and
the second type of line is above a bottom surface of the plurality of first type of lines.
16 . The semiconductor structure of claim 14 , wherein the second type of line each connect by one via of a plurality of second vias to an element from the group consisting of: (i) a semiconductor device and (ii) a metal level that is under the first metal level.
17 . The semiconductor structure of claim 16 , further comprising:
the second type of line each connect by one of the plurality of second vias to a semiconductor device of a plurality of semiconductor devices;
the semiconductor device of the plurality of semiconductor devices connects by a through-silicon via to a third via under a backside of a semiconductor substrate; and
the third via connects to a backside second type of line in a first backside metal level.
18 . The semiconductor structure of claim 14 , further comprising:
a third front side metal level above the second front side metal level including a second plurality of first type of lines and another second type of line between two adjacent first type of lines of the second plurality of first type of lines.
19 . The semiconductor structure of claim 14 , wherein:
the second type of line includes more than one of the second type of line; and
each of the more than one of the second type of line is selected from the group of second type of lines consisting of: has a top surface that is above the top surface of the plurality of first type of lines, has a top surface that is level with a middle portion of the plurality of first type of lines, and has a top surface that is level with the top surface of the plurality of first type of lines.
20 . The semiconductor structure of claim 14 , wherein the first front side metal level is a metal level selected from the group consisting of: a middle-of-line metal level and a back-end-of-line metal level.
21 . A semiconductor structure comprising:
a plurality of first type of lines in a first front side metal level with a first type of line width;
a second type of line in the first front side metal level with a second line width that is less than the first type of line width, wherein a single line of the second type of line is an only line separating two adjacent first type of lines of the plurality of first type of lines;
a plurality of first vias connecting a plurality of semiconductor devices to lines in the first front side metal level;
a plurality of through-silicon vias in a semiconductor substrate, wherein each of the plurality of through-silicon vias connect of the plurality of semiconductor devices to a plurality of second vias in a first dielectric layer on a backside of the semiconductor substrate;
a plurality of backside first type of lines in a first backside metal level with a third line width, wherein each of the plurality of backside first type of lines contact to one of the plurality of second vias;
a backside second type of line in the first backside metal level with a fourth line width that is narrower than the third line width, wherein:
the backside second type line is between two adjacent lines of the plurality of backside first type of lines; and
the backside second type of line contacts one via of the plurality of second vias; and
a plurality of third vias connecting the backside second type of line and the plurality of backside first type of lines to a second backside metal level.
22 . The semiconductor structure of claim 21 , wherein the backside second type of line has a same height as the plurality of backside first type of lines.
23 . The semiconductor structure of claim 21 , wherein the backside second type of line has a top surface with a level that is selected from the group consisting of: a lower level than a top surface of the plurality of backside first type of lines, a same level as a middle portion of the plurality of backside first type of lines, and a higher level than the top surface of the plurality of backside first type of lines.
24 . A method comprising:
forming a plurality of first vias in a first dielectric material on a backside of semiconductor substrate using a damascene process;
etching two first trenches for two first type of lines over a via of the plurality of first vias using the damascene process;
depositing a metal material in the two first trenches;
performing a chemical mechanical polish (CMP);
subsequent to depositing the metal material in the first two trenches, etching a third trench between the two first type of lines using a damascene process, wherein the third trench is narrower than the two first trenches;
filling the third trench with the metal material; and
performing CMP to form a second type line.
25 . The method of claim 24 , wherein the metal material in the two first trenches and the metal material filling the third trench are different metal materials.