Signal generator and emphasis switching method using signal generator
There are provided a signal generator capable of flexibly increasing the number of taps while realizing high-speed emphasis switching and an emphasis switching method using the signal generator. A signal generator includes: an emphasis addition circuit including at least one finite impulse response (FIR) filter unit that generates an emphasis waveform pattern by adding an emphasis to a pattern of a pulse amplitude modulation (PAM) signal including multi-values which are two or more values; and a tap value setting unit that switches M tap values C(0), C(−1), . . . , and C(1−M) and sets the M tap values C(0), C(−1), . . . , and C(1−M) to each FIR filter unit according to an emphasis switching request from a DUT 100 . The FIR filter unit is configured on an FPGA or an ASIC.
1. A signal generator comprising:
an emphasis addition circuit including at least one finite impulse response (FIR) filter unit that generates an emphasis waveform pattern by adding an emphasis to a pattern of a pulse amplitude modulation (PAM) signal including multi-values which are two or more values; and
a tap value setting unit that switches M tap values C(0), C(−1), . . . , and C(1−M) and sets the M tap values C(0), C(−1), . . . , and C(1−M) to the at least one FIR filter unit according to an emphasis switching request from a device under test,
wherein the at least one FIR filter unit includes:
a delay unit that respectively delays pieces of n-th to (n+M−1)-th data included in the pattern of the PAM signal by a predetermined delay amount with respect to the data immediately before each of the pieces of the (n+1)-th to (n+M−1)-th data and outputs the delayed data, and that respectively outputs the M tap values C(0), C(−1), . . . , and C(1−M) at the same timing as the pieces of the n-th to (n+M−1)-th data,
a plurality of multipliers that respectively multiply the pieces of the n-th to (n+M−1)-th data which are output from the delay unit by the M tap values C(0), C(−1), . . . , and C(1−M) which are output from the delay unit and output multiplied data, and
a plurality of adders that generate the emphasis waveform pattern based on an addition of output values of the plurality of multipliers, and
the at least one FIR filter unit is configured on a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC).
2. The signal generator according to claim 1 , wherein the emphasis addition circuit is configured by providing a plurality of circuit configurations of the at least one FIR filter unit in parallel, and outputs a plurality of pieces of data included in the emphasis waveform pattern at the same clock timing.
3. The signal generator according to claim 1 , wherein the tap value setting unit includes:
an emphasis setting table that stores a plurality of sets of the M tap values C(0), C(−1), . . . , and C(1−M) defined by a standard, and
an emphasis switching instruction unit that selects, from the emphasis setting table, the M tap values C(0), C(−1), . . . , and C(1−M) to be newly set to the at least one FIR filter unit according to the switching request from the device under test and outputs the selected M tap values C(0), C(−1), . . . , and C(1−M) from the emphasis setting table.
4. The signal generator according to claim 1 , wherein the plurality of multipliers and the plurality of adders are configured in a digital signal processor (DSP).
5. The signal generator according to claim 1 , further comprising:
an N-bit digital-to-analog converter (DAC) that outputs an analog signal according to the emphasis waveform pattern which is output from the emphasis addition circuit to the device under test, wherein N is a positive integer,
wherein the at least one FIR filter unit further includes an N-bit conversion unit that generates the emphasis waveform pattern by converting the output values of the plurality of multipliers, which are obtained after being added by the plurality of adders, into integer values within a range from 0 to 2 N −1.
6. An emphasis switching method comprising:
an emphasis addition step of generating an emphasis waveform pattern by adding an emphasis to a pattern of a pulse amplitude modulation (PAM) signal including multi-values which are two or more values by at least one finite impulse response (FIR) filter unit configured on a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC); and
a tap value setting step of switching M tap values C(0), C(−1), . . . , and C(1−M) and setting the M tap values C(0), C(−1), . . . , and C(1−M) to the at least one FIR filter unit according to an emphasis switching request from a device under test,
wherein the emphasis addition step includes:
a delay step of respectively delaying pieces of n-th to (n+M−1)-th data included in the pattern of the PAM signal by a predetermined delay amount with respect to the data immediately before each of the pieces of the (n+1)-th to (n+M−1)-th data and outputting the delayed data, and respectively outputting the M tap values C(0), C(−1), . . . , and C(1−M) at the same timing as the pieces of the n-th to (n+M−1)-th data,
a multiplication step of respectively multiplying the pieces of the n-th to (n+M−1)-th data which are output from the delay step by the M tap values C(0), C(−1), . . . , and C(1−M) which are output from the delay step and outputting multiplied data, and
an addition step of generating the emphasis waveform pattern based on an addition of output values of the multiplication step.
7. The emphasis switching method according to claim 6 , wherein the emphasis addition step further includes outputting a plurality of pieces of data included in the emphasis waveform pattern at the same clock timing.
8. The emphasis switching method according to claim 6 , wherein the tap value setting step includes selecting, from an emphasis setting table that stores a plurality of sets of the M tap values C(0), C(−1), . . . , and C(1−M) defined by a standard, the M tap values C(0), C(−1), . . . , and C(1−M) to be newly set to the at least one FIR filter unit according to the emphasis switching request from the device under test and outputting the selected M tap values C(0), C(−1), . . . , and C(1−M) from the emphasis setting table.