Ferroelectric memory device and method of forming the same
The present disclosure, in some embodiments, relates to a ferroelectric memory device. The ferroelectric memory device includes a multi-layer stack disposed on a substrate. The multi-layer stack has a plurality of conductive layers and a plurality of dielectric layers stacked alternately. A channel layer penetrates through the plurality of conductive layers and the plurality of dielectric layers. A ferroelectric layer is disposed between the channel layer and both of the plurality of conductive layers and the plurality of dielectric layers. A plurality of oxygen scavenging layers are disposed along sidewalls of the plurality of conductive layer. The plurality of oxygen scavenging layers laterally separate the ferroelectric layer from the plurality of conductive layers.
1. A ferroelectric memory device, comprising:
a multi-layer stack disposed on a substrate and comprising a plurality of conductive layers and a plurality of dielectric layers stacked alternately;
a channel layer penetrating through the plurality of conductive layers and the plurality of dielectric layers;
a ferroelectric layer disposed between the channel layer and both of the plurality of conductive layers and the plurality of dielectric layers; and
a plurality of oxygen scavenging layers disposed along sidewalls of the plurality of conductive layers, wherein the plurality of oxygen scavenging layers laterally separate the ferroelectric layer from the plurality of conductive layers.
2. The ferroelectric memory device of claim 1 , wherein ends of the conductive layers are recessed from ends of the dielectric layers.
3. The ferroelectric memory device of claim 1 , wherein sidewalls of the oxygen scavenging layers are substantially flush with sidewalls of the plurality of dielectric layers.
4. The ferroelectric memory device of claim 1 , wherein the plurality of oxygen scavenging layers are respectively disposed between adjacent ones of the plurality of dielectric layers.
5. The ferroelectric memory device of claim 1 , wherein the channel layer comprises zinc oxide (ZnO), indium tungsten oxide (InWO), indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium tin oxide (ITO), or a combination thereof.
6. The ferroelectric memory device of claim 1 , further comprising:
an interfacial layer between the channel layer and the ferroelectric layer, an oxygen content of the interfacial layer being greater than an oxygen content of the channel layer.
7. The ferroelectric memory device of claim 6 , wherein the ferroelectric layer continuously and vertically extends past two or more of the plurality of oxygen scavenging layers.
8. A ferroelectric memory device, comprising:
a multi-layer stack disposed on a substrate and comprising a plurality of gate electrode layers and a plurality of dielectric layers stacked alternately;
a plurality of dielectric pillars disposed on the substrate and penetrating through the multi-layer stack;
an oxide semiconductor layer comprising a first metal element and disposed between the multi-layer stack and each of the plurality of dielectric pillars; and
a ferroelectric layer disposed between the oxide semiconductor layer and the multi-layer stack; and
a plurality of oxygen scavenging layers comprising a second metal element, one of the plurality of oxygen scavenging layers disposed between the ferroelectric layer and each of the plurality of gate electrode layers.
9. The ferroelectric memory device of claim 8 , wherein the ferroelectric layer continuously extends past two or more of the plurality of oxygen scavenging layers.
10. The ferroelectric memory device of claim 8 , further comprising:
a second plurality of dielectric pillars disposed on the substrate and penetrating through the multi-layer stack;
a second oxide semiconductor layer disposed between the multi-layer stack and each of the second plurality of dielectric pillars;
a second ferroelectric layer disposed between the second oxide semiconductor layer and the multi-layer stack; and
second plurality of oxygen scavenging layers disposed between the second ferroelectric layer and each of the plurality of gate electrode layers.
11. The ferroelectric memory device of claim 8 , wherein the plurality of oxygen scavenging layers further comprise an oxygen element.
12. The ferroelectric memory device of claim 8 , wherein an oxygen density in the plurality of oxygen scavenging layers is increased towards the ferroelectric layer.
13. The ferroelectric memory device of claim 8 , wherein a Gibb's free energy of an oxide of the second metal element is less than a Gibb's free energy of an oxide of the first metal element.
14. The ferroelectric memory device of claim 8 , wherein the plurality of dielectric layers vertically separate adjacent ones of the plurality of oxygen scavenging layers.
15. The ferroelectric memory device of claim 8 , wherein an interface between the oxide semiconductor layer and the ferroelectric layer is substantially free of oxygen atoms.
16. The ferroelectric memory device of claim 8 , further comprising:
a plurality of conductive pillars disposed on the substrate and penetrating through the multi-layer stack, wherein each of the plurality of dielectric pillars has two conductive pillars disposed along opposing sides thereof.
17. A ferroelectric memory device, comprising:
a plurality of dielectric layers alternatively stacked with a plurality of conductive layers;
an oxide semiconductor layer disposed along sides of the plurality of conductive layers and the plurality of dielectric layers;
a ferroelectric layer disposed along a sidewall of the oxide semiconductor layer; and
a plurality of oxygen scavenging layers disposed vertically between adjacent ones of the plurality of dielectric layers and laterally between the ferroelectric layer and each of the plurality of conductive layers, wherein a center of a first oxygen scavenger layer of the plurality of oxygen scavenging layers is directly below a lower surface of an overlying one of the plurality of dielectric layers.
18. The ferroelectric memory device of claim 17 , wherein the first oxygen scavenger layer physically contacts one of the plurality of conductive layers.
19. The ferroelectric memory device of claim 17 , wherein the first oxygen scavenger layer has an outermost sidewall that faces away from a closest one of the plurality of conductive layers, the outermost sidewall of the first oxygen scavenger layer being laterally aligned with an outermost sidewall of the plurality of dielectric layers.
20. The ferroelectric memory device of claim 17 , wherein the first oxygen scavenger layer physically contacts the adjacent ones of the plurality of dielectric layers.