Ferroelectric memory device and method of forming the same
A device includes a multi-layer stack, a channel layer, a ferroelectric layer and buffer layers. The multi-layer stack is disposed on a substrate and includes a plurality of conductive layers and a plurality of dielectric layers stacked alternately. The channel layer penetrates through the plurality of conductive layers and the plurality of dielectric layers. The ferroelectric layer is disposed between the channel layer and each of the plurality of conductive layers and the plurality of dielectric layers. The buffer layers include a metal oxide, and one of the buffer layers is disposed between the ferroelectric layer and each of the plurality of dielectric layers.
1. A method of forming a device, comprising:
forming a multi-layer stack on a substrate, wherein the multi-layer stack comprises dielectric layers and conductive layers stacked alternately and has a trench penetrating therethrough;
recessing the dielectric layers exposed by a sidewall of the trench and therefore forming recesses, one of the recesses formed between two adjacent conductive layers;
forming buffer layers within the recesses, respectively, wherein the buffer layers are in physical contact with the dielectric layers, respectively;
forming a ferroelectric layer on the sidewall of the trench, wherein the ferroelectric layer covers sidewalls of the buffer layers and sidewalls of the conductive layers; and
forming a channel layer on the ferroelectric layer.
2. The method of claim 1 , further comprising, after forming the buffer layers and before forming the ferroelectric layer, performing an annealing process to the buffer layers.
3. The method of claim 2 , wherein a temperature range of the annealing process ranges from about 300° C. to about 450° C.
4. The method of claim 1 , wherein recessing the dielectric layers comprises performing an etching process.
5. The method of claim 1 , wherein forming the buffer layers comprises:
forming a buffer material conformally and continuously on a sidewall of the multi-layer stack, wherein the buffer material fills in the recesses; and
performing an etching back process to the buffer material.
6. The method of claim 5 , wherein after the etching back process, a sidewall of each buffer layer is flushed with a sidewall of the adjacent conductive layer.
7. The method of claim 5 , wherein after the etching back process, a sidewall of each buffer layer is recessed from a sidewall of the adjacent conductive layer by a non-zero distance.
8. The method of claim 1 , wherein the buffer layers comprise metal oxide.
9. A method of forming a device, comprising:
providing a multi-layer stack on a substrate, wherein the multi-layer stack comprises dielectric layers and conductive layers stacked alternately;
trimming the dielectric layers until sidewalls of the conductive layers are protruded from sidewalls of the trimmed dielectric layers;
forming buffer layers on the sidewalls of the trimmed dielectric layers, wherein the buffer layers are in physical contact with the dielectric layers, respectively;
forming a ferroelectric layer on sidewalls of the buffer layers and the sidewalls of the conductive layers; and
forming a channel layer on the ferroelectric layer.
10. The method of claim 9 , wherein trimming the dielectric layers comprises performing a lateral etching process.
11. The method of claim 9 , wherein forming the buffer layers comprises:
forming a continuous buffer material on the sidewalls of the trimmed dielectric layers and the sidewalls of the conductive layers; and
performing an etching process to the continuous buffer material, so as to divide the continuous buffer material into the buffer layers respectively on the sidewalls of the trimmed dielectric layers.
12. The method of claim 11 , wherein the continuous buffer material is in an amorphous state.
13. The method of claim 12 , further comprising performing an annealing process to transform the continuous buffer material into a crystalline state.
14. The method of claim 11 , wherein the continuous buffer material is in a crystalline state.
15. The method of claim 9 , wherein a bottom of the ferroelectric layer is flushed with a bottom of the lowermost buffer layer.
16. The method of claim 9 , wherein the ferroelectric layer has substantially smooth sidewall profile.
17. The method of claim 9 , wherein the ferroelectric layer has an uneven and wavy sidewall profile.
18. A method of forming a device, comprising:
providing a substrate having a cell region and a staircase region;
forming a first multi-layer stack on the substrate in the cell region and forming a second multi-layer stack on the substrate in the staircase region, wherein each of the first multi-layer stack and the second multi-layer stack comprises dielectric layers and conductive layers stacked alternately;
trimming the dielectric layers of the first multi-layer stack in the cell region without trimming the dielectric layers of the second multi-layer stack in the staircase region;
forming buffer layers on the sidewalls of the trimmed dielectric layers of the first multi-layer stack in the cell region;
forming a ferroelectric layer on sidewalls of the buffer layers and the sidewalls of the conductive layers in the cell region; and
forming a channel layer on the ferroelectric layer in the cell region.
19. The method of claim 18 , further comprising patterning the second multi-layer stack in the staircase region, such that ends of the conductive layers and ends of the insulating layers of the second multi-layer stack are arranged in a staircase configuration.
20. The method of claim 18 , wherein each of the buffer layers and the ferroelectric layer comprises metal oxide.