High-k isolation of fin structures

1 . A method comprising:

forming fin structures separated by an isolation material;

selectively growing a semiconductor liner over the fin structures;

depositing a high-k material over the fin structures and the isolation material, wherein the high-k material includes lower portions located between the fin structures and includes an upper portion located above the fin structures;

depositing a capping layer over the high-k material; and

performing a planarization process to remove the capping layer and the upper portion of the high-k material and to define high-k insulation segments.

2 . The method of claim 1 , wherein the high-k material is hafnium oxide.

3 . The method of claim 1 , wherein depositing the high-k material comprises forming a multi-layer structure comprised of layers of hafnium oxide and interposing uniformity-improving layers.

4 . The method of claim 1 , wherein the high-k material is hafnium oxide and the capping layer is silicon oxide.

5 . The method of claim 1 , wherein the planarization process comprises

a first stage selective to etching the capping layer and that lands on the high-k material;

a second stage selective to etching the high-k material and that lands on the fin structures; and

a third stage that is non-selective.

6 . The method of claim 1 , wherein the planarization process provides a controlled pH to increase a removal rate of the high-k material while suppressing a removal rate of the fin structures.

7 . The method of claim 1 , wherein the planarization process uses a slurry formula comprising silica abrasive and HNO 3 , and wherein a pH of the slurry formula is from about 1 to about 5.

8 . The method of claim 1 , further comprising:

removing the semiconductor liner and a top layer from each fin structure to form each fin structure with an uppermost surface located at a height below an upper surface of the high-k insulation segments; and

forming a metal gate over each fin structure and between the high-k insulation segments.

9 . A method comprising:

forming a fin structure, wherein the fin structure comprises an epitaxial stack including alternating layers of a first semiconductor material and a second semiconductor material;

forming a high-k isolation region laterally adjacent to the fin structure, wherein the high-k isolation region has an upper surface; and

removing a top layer of the second semiconductor material of the fin structure to form the fin structure with an uppermost surface located at a height below the upper surface of the high-k isolation region.

10 . The method of claim 9 , wherein the method further comprises:

forming a sacrificial gate over the uppermost surface of the fin structure;

depositing a dielectric material around the sacrificial gate;

removing the sacrificial gate;

removing layers of the second semiconductor material, wherein layers of the first semiconductor material remain; and

forming a metal gate around and over the layers of the first semiconductor material.

11 . The method of claim 9 , wherein the high-k isolation region comprises hafnium oxide.

12 . The method of claim 9 , wherein forming the high-k isolation region comprises forming a multi-layer structure comprised of layers of hafnium oxide and interposing uniformity-improving layers.

13 . The method of claim 9 , wherein forming the high-k isolation region comprises forming a multi-layer structure comprised of layers of hafnium oxide and interposing silicon oxide layers.

14 . The method of claim 9 , wherein forming the high-k isolation region comprises:

depositing hafnium oxide over and around the epitaxial stack of the fin structure;

forming a capping layer over the hafnium oxide; and

performing a chemical mechanical planarization (CMP) process to remove the capping layer and an upper portion of the hafnium oxide and to form the high-k isolation region with an upper surface coplanar with the top layer.

15 . A semiconductor device comprising:

a fin structure;

a gate structure located over the fin structure; and

a hafnium oxide region laterally adjacent to the fin structure, wherein the hafnium oxide region comprises alternating layers of hafnium oxide and a uniformity-improving material.

16 . The semiconductor device of claim 15 , wherein:

the fin structure comprises spaced apart nanosheets of semiconductor material including an upper nanosheet defining an uppermost surface of the fin structure;

the gate structure is located between and above the nanosheets;

the hafnium oxide region has a top surface at a height above the uppermost surface of the fin structure; and

the hafnium oxide region has a bottom surface that is non-planar.

17 . The semiconductor device of claim 15 , wherein:

the fin structure is a hybrid fin structure comprising SiCN and having an uppermost surface; and

the hafnium oxide region has a top surface substantially co-planar with the uppermost surface of the fin structure.

18 . The semiconductor device of claim 15 , wherein the uniformity-improving material comprises silicon oxide.

19 . The semiconductor device of claim 15 , wherein the hafnium oxide region comprises alternating layers of hafnium oxide and silicon oxide.

20 . The semiconductor device of claim 15 , wherein:

the hafnium oxide region comprises alternating layers of hafnium oxide and silicon oxide;

the hafnium oxide region has a top surface; and

the top surface is formed by at least two layers of hafnium oxide and at least one layer of silicon oxide.