Integrated circuit including integrated standard cell structure
An integrated circuit including a first active region and a second active region extending in a first direction and spaced apart from each other in a second direction intersecting the first direction; a power rail and a ground rail extending in the first direction and spaced apart from the first and second active regions and each other in the second direction; source/drain contacts extending in the second direction on at least a portion of the first or second active region, gate structures extending in the second direction and on at least a portion of the first and second active regions, a power rail configured to supply power through source/drain contact vias, and a ground rail configured to supply a ground voltage through source/drain contact vias.
1. An integrated circuit comprising:
a first inverter including a first p-channel metal-oxide-semiconductor (PMOS) transistor and a first n-channel metal-oxide-semiconductor (NMOS) transistor, which are gated through a first metal line to which a first input voltage is configured to be applied, and configured to output a first inverted voltage by inverting the first input voltage, wherein a drain of the first NMOS transistor and a drain of the first PMOS transistor are routed through a first source/drain contact, a first metal line extends in a first direction, and the first source/drain contact extends in a second direction perpendicular to the first direction;
a first transmission gate including a second PMOS transistor gated through a second metal line to which a first active voltage is configured to be applied and a second NMOS transistor gated through a third metal line to which a second active voltage is configured to be applied, wherein a source of the second PMOS transistor and a drain of the second NMOS transistor are routed through the first source/drain contact, and a drain of the second PMOS transistor and a source of the second NMOS transistor are routed through a second source/drain contact; and
a first tri-state inverter including a third PMOS transistor gated through a fourth metal line to which the second active voltage is configured to be applied, a third NMOS transistor gated through a fifth metal line to which the first active voltage is configured to be applied, and a fourth PMOS transistor and a fourth NMOS transistor, which are gated through a sixth metal line to which a second input voltage is configured to be applied, and configured to invert the second input voltage, wherein a drain of the third PMOS transistor and a drain of the third NMOS transistor are routed through the second source/drain contact.
2. The integrated circuit of claim 1 , further comprising:
a first active region extending in the first direction and including the first to fourth PMOS transistors;
a second active region extending in the first direction and including the first to fourth NMOS transistors;
a power rail extending in the first direction and configured to supply a power voltage to the first PMOS transistor and the fourth PMOS transistor; and
a ground rail extending in the first direction and configured to supply a ground voltage to the first NMOS transistor and the fourth NMOS transistor,
wherein the first active region and the second active region are spaced apart from each other by a first distance in the second direction intersecting the first direction,
the first active region and the power rail are spaced apart from each other by a second distance in the second direction, and
the second active region and the ground rail are spaced apart from each other by a third distance in the second direction.
3. The integrated circuit of claim 2 , wherein the second distance is equal to the third distance.
4. The integrated circuit of claim 2 , wherein a sum of the second distance and the third distance is greater than the first distance.
5. The integrated circuit of claim 2 , wherein a sum of the second distance and the third distance is less than the first distance.
6. The integrated circuit of claim 1 , further comprising:
a first gate contact configured to apply the first input voltage to the first metal line;
a second gate contact configured to apply the first active voltage to the second metal line;
a third gate contact configured to apply the second active voltage to the third metal line;
a fourth gate contact configured to apply the second active voltage to the fourth metal line;
a fifth gate contact configured to apply the first active voltage to the fifth metal line; and
a sixth gate contact configured to apply the second input voltage to the sixth metal line.
7. The integrated circuit of claim 6 , wherein heights of the second gate contact and the fourth gate contact in the second direction are equal to each other.
8. The integrated circuit of claim 6 , wherein heights of the second gate contact and the fourth gate contact in the second direction are different from each other.
9. The integrated circuit of claim 6 , wherein heights of the fourth gate contact and the sixth gate contact in the second direction are different from each other.
10. The integrated circuit of claim 6 , wherein heights of the fourth gate contact and the sixth gate contact in the second direction are equal to each other.
11. The integrated circuit of claim 6 , wherein heights of the first gate contact and the sixth gate contact in the second direction are different from each other.
12. The integrated circuit of claim 1 , further comprising:
a first active region extending in the first direction and including the first to fourth PMOS transistors, wherein a first gate contact configured to apply the first input voltage to the first metal line, a second gate contact configured to apply the first active voltage to the second metal line, and a fourth gate contact configured to apply the second active voltage to the fourth metal line are on the first active region;
a second active region extending in the first direction and including the first to fourth NMOS transistors, wherein a third gate contact configured to apply the second active voltage to the third metal line, a fifth gate contact configured to apply the first active voltage to the fifth metal line, and a sixth gate contact configured to apply the second input voltage to the sixth metal line are on the second active region;
a power rail extending in the first direction and configured to supply a power voltage to the first PMOS transistor and the fourth PMOS transistor; and
a ground rail extending in the first direction and configured to supply a ground voltage to the first NMOS transistor and the fourth NMOS transistor,
wherein the first active region and the power rail are spaced apart from each other by a first distance in the second direction, and
the second active region and the ground rail are spaced apart from each other by a second distance in the second direction.
13. The integrated circuit of claim 12 , wherein
the power rail and the first gate contact are spaced apart from each other by a third distance in the second direction,
the power rail and the second gate contact are spaced apart from each other by a fourth distance in the second direction,
the power rail and the fourth gate contact are spaced apart from each other by a fifth distance in the second direction, and
the shortest distance among the third to fifth distances is greater than the first distance.
14. The integrated circuit of claim 12 , wherein
the power rail and the third gate contact are spaced apart from each other by a third distance in the second direction,
the power rail and the fifth gate contact are spaced apart from each other by a fourth distance in the second direction,
the power rail and the sixth gate contact are spaced apart from each other by a fifth distance in the second direction, and
the shortest distance among the third to fifth distances is greater than the second distance.