Transistor contacts and methods of forming thereof
A device includes a first transistor layer comprising a first gate electrode and a second transistor layer comprising a second gate electrode that is stacked with the first transistor layer. n intermetal structure comprising a conductive line is disposed between the first transistor layer and the second transistor layer. A first gate contact extends along a sidewall of the first gate electrode from a top surface of the first gate electrode to the conductive line 48 G. A second gate contact extends along a sidewall of the second gate electrode from a top surface of the second gate electrode to the conductive line. The first gate electrode is electrically connected to the second gate electrode by the first gate contact, the second gate contact, and the conductive line.
1 . A device comprising:
a first transistor layer comprising a first gate electrode;
a second transistor layer comprising a second gate electrode;
an intermetal structure between the first transistor layer and the second transistor layer, the intermetal structure comprising a first conductive line;
a first gate contact extending along a sidewall of the first gate electrode from a top surface of the first gate electrode to the first conductive line; and
a second gate contact extending along a sidewall of the second gate electrode from a top surface of the second gate electrode to the first conductive line, wherein the first gate electrode is electrically connected to the second gate electrode by the first gate contact, the second gate contact, and the first conductive line.
2 . The device of claim 1 , wherein the first gate contact and the second gate contact each comprise tungsten (W), cobalt (Co), or ruthenium (Ru).
3 . The device of claim 1 , wherein the first conductive line is disposed in a dielectric layer, wherein the first transistor layer further comprises a third gate electrode, and wherein the device further comprises a third gate contact extending along a sidewall of the third gate electrode from a top surface of the third gate electrode to the dielectric layer.
4 . The device of claim 3 , wherein the dielectric layer covers an entire lateral surface of the third gate contact.
5 . The device of claim 1 , wherein the first transistor layer further comprises a first source/drain region, wherein the second transistor layer further comprises a second source/drain region, wherein the intermetal structure comprises a second conductive line, and wherein the device further comprises:
a first source/drain contact extending through the first source/drain region to the second conductive line; and
a second source/drain contact extending through the second source/drain region to the second conductive line, wherein the first source/drain region is electrically connected to the second source/drain region by the first source/drain contact, the second conductive line, and the second source/drain contact.
6 . The device of claim 1 , wherein the intermetal structure comprises:
a dielectric layer, wherein the first conductive line is disposed in the dielectric layer;
a first etch stop layer, wherein the first gate contact extends through the first etch stop layer; and
a second etch stop layer, wherein the second gate contact extends through the second etch stop layer, and wherein the dielectric layer is disposed between the first etch stop layer and the second etch stop layer.
7 . The device of claim 1 further comprising a first bonding layer directly bonded to a second bonding layer by a dielectric-to-dielectric bond, the first bonding layer and the second bonding layer being disposed between the first transistor layer and the intermetal structure.
8 . A device comprising:
a first source/drain region in a first transistor layer;
a first conductive line in a dielectric layer over the first source/drain region;
a second source/drain region over the first conductive line, the second source/drain region being disposed in a second transistor layer;
a first source/drain contact extending through the first source/drain region and touching the first conductive line;
a first silicide region on a sidewall of the first source/drain contact and a sidewall of the first source/drain region;
a second source/drain contact extending through the second source/drain region and touching the first conductive line, wherein the first source/drain region is electrically connected to the second source/drain region by the first source/drain contact, the second source/drain contact, and the first conductive line; and
a second silicide region on a sidewall of the second source/drain contact and a sidewall of the second source/drain region.
9 . The device of claim 8 , wherein the first source/drain contact and the second source/drain contact each comprises tungsten (W), cobalt (Co), or ruthenium (Ru).
10 . The device of claim 8 , further comprising:
a third source/drain contact electrically connected to the first source/drain region, wherein the first source/drain contact extends through the third source/drain contact; and
a fourth source/drain contact electrically connected to the second source/drain region, wherein the second source/drain contact extends through the fourth source/drain contact.
11 . The device of claim 10 , wherein the first source/drain contact has a different material composition than the third source/drain contact, and wherein the second source/drain contact has a different material composition than the fourth source/drain contact.
12 . The device of claim 8 further comprising:
a first gate electrode in the first transistor layer;
a second gate electrode in the second transistor layer;
a second conductive line in the dielectric layer;
a first gate contact extending through the first gate electrode to the second conductive line; and
a second gate contact extending through the second gate electrode to the second conductive line, wherein the first gate electrode is electrically connected to the second gate electrode by the first gate contact, the second gate contact, and the second conductive line.
13 . The device of claim 8 further comprising:
a first gate electrode in the first transistor layer;
a second gate electrode in the second transistor layer; and
a gate contact extending through the first gate electrode, the dielectric layer, and the second gate electrode, wherein the first gate electrode is electrically connected to the second gate electrode by the gate contact.
14 . A device comprising:
a first gate electrode disposed in a first transistor layer;
a second gate electrode disposed in a second transistor layer, wherein the first transistor layer and the second transistor layer are vertically stacked;
an interconnect structure between the first transistor layer and the second transistor layer, the interconnect structure comprising a first conductive line;
a first gate contact electrically connected to the first gate electrode, wherein the first gate contact extends through the first gate electrode; and
a second gate contact electrically connected to the second gate electrode, wherein the first conductive line extends from a surface of the first gate contact to a surface of the second gate contact, and wherein the second gate contact extends through the second gate electrode.
15 . The device of claim 14 , wherein the first gate contact decreases in width in a first direction towards the first conductive line, and wherein the second gate contact decreases in width in a second direction towards the first conductive line.
16 . The device of claim 14 further comprising:
a first source/drain region in the first transistor layer;
a second source/drain region in the second transistor layer;
a first source/drain contact electrically connected to the first source/drain region; and
a second source/drain contact electrically connected to the second source/drain region, wherein a second conductive line in the interconnect structure electrically connects the first source/drain contact to the second source/drain contact.
17 . The device of claim 16 , wherein the first source/drain contact extends through the first source/drain region, and wherein the second source/drain contact extends through the second source/drain region.
18 . The device of claim 16 , wherein the first conductive line and the second conductive line are disposed in a same dielectric layer of the interconnect structure.
19 . The device of claim 14 further comprising an isolation structure along a sidewall of the first gate electrode, wherein the first gate contact contacts the isolation structure.
20 . The device of claim 14 further comprising:
a first insulating bonding layer on the first transistor layer; and
a second insulating bonding layer on the interconnect structure, wherein the first insulating bonding layer is bonded to the second insulating bonding layer by dielectric-to-dielectric bonds.