IP Library › Granted Patent US 12,557,662
Granted Patent B2
US 12,557,662 · App. 18/357,704 · Granted Feb 17, 2026

Manufacturing method of semiconductor structure

Inventors: Feng-Wei Kuo (Hsinchu, TW); Wen-Shiang Liao (Hsinchu, TW)
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
H01L23/66H01L21/4853H01L21/4857H01L21/565H01L21/568H01L21/6835H01L23/3128H01L23/5383H01L23/5386H01L23/5389H01L24/19H01L24/20H01Q1/52H01Q9/0407H01L2221/68372H01L2223/6677H01L2224/214
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Quick Facts
Patent No.
US 12,557,662
App. No.
18/357,704
Granted
Feb 17, 2026
Kind
B2
Abstract

A method of forming a semiconductor structure includes forming a photoresist over a first conductive pattern. The method further includes patterning the photoresist to define a plurality of first openings. The method further includes depositing a conductive material in each of the plurality of first openings. The method further includes disposing a molding material over the first conductive pattern, wherein the molding material surrounds a die. The method further includes removing a portion of the molding material to form a second opening. The method further includes disposing a dielectric material into the opening to form a dielectric member. The method further includes forming a redistribution structure over the molding material and the dielectric member, wherein the redistribution structure includes an antenna structure over the dielectric member and electrically connected to the die.

Claims (42)

1 . A method of forming a semiconductor structure, comprising:

forming a photoresist over a first conductive pattern;

patterning the photoresist to define a plurality of first openings;

depositing a conductive material in each of the plurality of first openings;

disposing a molding material over the first conductive pattern, wherein the molding material surrounds a die;

removing a portion of the molding material to form a second opening;

disposing a dielectric material into the opening to form a dielectric member; and

forming a redistribution structure over the molding material and the dielectric member, wherein the redistribution structure includes an antenna structure over the dielectric member and electrically connected to the die, wherein forming the redistribution structure comprises forming the antenna structure overlapping the conductive material in each of the plurality of openings in a plan view.

2 . The method of claim 1 , wherein a composition of the dielectric material is different from a composition of the molding material.

3 . The method of claim 1 , wherein forming the redistribution structure comprises forming the antenna structure offset with respect to the die in the plan view.

4 . The method of claim 1 , further comprising:

forming a conductive bump over the redistribution structure.

5 . A method of forming a semiconductor structure, comprising:

forming a first redistribution structure including a first conductive pattern;

disposing a molding material over the first redistribution structure, wherein a bottom surface of the molding material is co-planar with a bottom surface of the first redistribution structure;

patterning the molding material to define an opening;

depositing a dielectric material into the opening to form a dielectric member; and

forming a second redistribution structure over the molding material and the dielectric member, wherein the second redistribution structure includes an antenna structure surrounding the dielectric member in a plan view.

6 . The method of claim 5 , further comprising placing a die over the first redistribution structure.

7 . The method of claim 6 , wherein patterning the molding material comprises forming the opening separated from the die.

8 . The method of claim 6 , wherein forming the second redistribution structure comprises electrically connecting the antenna structure to the die.

9 . The method of claim 6 , further comprising forming a plurality of conductive bumps over the second redistribution structure.

10 . The method of claim 9 , further comprising electrically connecting a first conductive bump of the plurality of conductive bumps to the die.

11 . The method of claim 9 , wherein forming the plurality of conductive bumps comprises forming each of the plurality of conductive bumps offset from the antenna structure in a plan view.

12 . The method of claim 5 , further comprising:

forming a photoresist over the first redistribution structure;

patterning the photoresist to define a plurality of first openings; and

depositing a conductive material in each of the plurality of first openings.

13 . A method of forming a semiconductor structure, comprising:

placing a die over a first redistribution structure;

forming a plurality of conductive vias over the first redistribution structure, wherein each of the plurality of conductive vias lands on the first redistribution structure;

disposing a dielectric material into an opening between adjacent conductive vias of the plurality of conductive vias, wherein at least one conductive via of the plurality of conductive vias is between the die and the dielectric material; and

forming a second redistribution structure over the molding material, wherein the second redistribution structure includes an antenna structure over the dielectric member, wherein forming the second redistribution structure comprises forming the antenna structure overlapping the dielectric material and each of the plurality of conductive vias in a plan view.

14 . The method of claim 13 , further comprising electrically connecting the antenna structure to the die.

15 . The method of claim 13 , further comprising forming a bump structure over the second redistribution structure.

16 . The method of claim 15 , further comprising electrically connecting the bump structure to the die.

17 . The method of claim 13 , wherein forming the second redistribution structure comprises forming the antenna structure offset with respect to the die in the plan view.

18 . The method of claim 13 , wherein forming the second redistribution structure comprises forming the antenna structure surrounded by the first redistribution structure in a plan view.

19 . The method of claim 13 , further comprising disposing a molding material between the die and the plurality of conductive vias.

20 . The method of claim 19 , wherein disposing the dielectric material comprises:

etching the molding material to define an opening between adjacent conductive vias of the plurality of conductive vias; and

depositing the dielectric material in the opening.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 24, 2023
From: KUO, FENG-WEI; LIAO, WEN-SHIANG
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 064361/0231 →
Continuity (3)
Division 17118017 · Dec 10, 2020
Provisional Application 63011441 · Apr 17, 2020
Related Publication 20230395535A1 · Dec 7, 2023
References Cited (22)
US 7335986B1 · Paek et al. · 2008 [cited by applicant]
US 9431369B2 · Chih et al. · 2016 [cited by applicant]
US 10468763B2 · Yokoyama et al. · 2019 [cited by applicant]
US 20080029886A1 · Cotte et al. · 2008 [cited by applicant]
US 20130292808A1 · Yen et al. · 2013 [cited by applicant]
US 20160218072A1 · Liao et al. · 2016 [cited by applicant]
US 20170033062A1 · Liu et al. · 2017 [cited by applicant]
US 20170162524A1 · Wang · 2017 [cited by examiner]
US 20170271264A1 · Lee · 2017 [cited by applicant]
US 20180061698A1 · Tsai et al. · 2018 [cited by applicant]
US 20180166396A1 · Lee et al. · 2018 [cited by applicant]
US 20180337136A1 · Han et al. · 2018 [cited by applicant]
US 20200273773A1 · Wan · 2020 [cited by examiner]
US 20200295453A1 · Kuo et al. · 2020 [cited by applicant]
US 20210098860A1 · Kuo · 2021 [cited by examiner]
CN 107078406A · 2017 [cited by applicant]
CN 108807347 · 2018 [cited by applicant]
CN 109585428 · 2019 [cited by applicant]
JP 2007180704A · 2007 [cited by applicant]
TW I512907B · 2015 [cited by applicant]
Notice of Allowance dated Aug. 20, 2021 for corresponding application No. TW 11020811860. (pp. 1-3). [cited by applicant]
Search Report dated Aug. 19, 2021 for corresponding application No. JP 110108168. (p. 1). [cited by applicant]