IP Library Granted Patent US 12,282,318
Granted Patent B2
US 12,282,318 · App. 18/362,037 · Granted Apr 22, 2025

Semiconductor wafer cooling

Inventors: Yung-Yao Lee (Zhubei, TW); Cheng-Kang Hu (Kaohsiung, TW); Jui-Chun Peng (Hsinchu, TW); Hsu-Shui Liu (Pingjhen, TW)
Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
G05B19/41875G06T7/13G06T7/62G05B2219/45027G05B2219/45028G05B2219/45031G05B2219/45183G06T2207/30148
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,282,318
App. No.
18/362,037
Granted
Apr 22, 2025
Kind
B2
Abstract

A cooling controller receives, from one or more sensors, wafer information associated with a wafer. The cooling controller determines a pattern mask area for the wafer based on the wafer information. The cooling controller determines a cooling time for the wafer based on the pattern mask area. The cooling controller causes a cooling plate to cool the wafer for a time duration equal to the cooling time. Determining the cooling time for a wafer based on a pattern mask area provides stable and consistent wafer temperatures for wafers having different mask and layout properties, which reduces mask overlay variation and increases wafer yield.

Claims (64)

1. A method, comprising:

receiving, by a cooling controller, wafer information associated with a wafer from one or more sensors;

determining, by the cooling controller and based on the wafer information, a center point of the wafer,

wherein the center point of the wafer is based on a plurality of edge points for the wafer;

determining, by the cooling controller and based on the center point, a plurality of field edge points for the wafer,

wherein a quantity of the plurality of edge points is different from a quantity of the plurality of field edge points;

determining, by the cooling controller, a pattern mask area based on the plurality of field edge points;

determining, by the cooling controller, a cooling time for the wafer based on the pattern mask area and exposure process information; and

causing, by the cooling controller, a cooling plate to cool the wafer for a time duration equal to the cooling time.

2. The method of claim 1 , further comprising:

determining the plurality of edge points based on an image scan of the wafer.

3. The method of claim 1 , wherein the plurality of edge points are equally spaced apart along a perimeter of the wafer.

4. The method of claim 1 , wherein determining the center point comprises:

determining respective vectors from each edge point of the plurality of edge points; and

determining a point of intersection of the respective vectors as the center point.

5. The method of claim 1 , wherein determining the plurality of field edge points comprises:

determining a first vector from the center point; and

determining a second vector from the center point and orthogonal to the first vector.

6. The method of claim 1 , wherein determining the pattern mask area based on the plurality of field edge points comprises:

determining connecting lines between adjacent field edge points, of the plurality of field edge points, to form an enclosed area around the center point.

7. The method of claim 6 , wherein determining the pattern mask area based on the plurality of field edge points further comprises:

determining the pattern mask area based on a length and a width of the enclosed area.

8. A method, comprising:

coating a wafer with a photoresist;

determining a cooling time for the wafer by:

determining a time adjustment based on a scaling factor applied to a pattern mask area for the wafer; and

applying the time adjustment to a default cooling time;

causing a cooling plate to cool the wafer for a time duration equal to the cooling time;

exposing the wafer to a radiation source to transfer a pattern from a photomask to the photoresist; and

developing the pattern transferred to the photoresist on the wafer.

9. The method of claim 8 , further comprising:

determining the pattern mask area based on a center point of the wafer.

10. The method of claim 8 , wherein determining the cooling time comprises:

determining the cooling time based on a mask field utilization for the wafer.

11. The method of claim 8 , wherein the time duration equal to the cooling time is shorter in than a time duration equal to the default cooling time.

12. The method of claim 8 , wherein causing the cooling plate to cool the wafer for the time duration comprises:

transmitting a cooling control signal to the cooling plate at a start of the cooling time.

13. The method of claim 8 , wherein causing the cooling plate to cool the wafer for the time duration further comprises:

transmitting another cooling control signal to the cooling plate at an end of the cooling time.

14. The method of claim 8 , further comprising:

determining the pattern mask area based on a plurality of field edge points for the wafer.

15. A system, comprising:

one or more sensors configured to:

generate an image scan of a wafer, and

provide the image scan to a cooling controller;

the cooling controller configured to:

receive information indicating a presence of the wafer on a cooling plate;

provide, to the one or more sensors and based on the information indicating the presence of the wafer on the cooling plate, an indication to generate the image scan;

determine a plurality of field edge points for the wafer based on the image scan,

determine a pattern mask area for the wafer based on the plurality of field edge points,

determine a time adjustment based on the pattern mask area,

determine a cooling time for the wafer based on the time adjustment, and

provide a signal to the cooling plate based on the cooling time; and

the cooling plate configured to cool the wafer for a time duration equal to the cooling time based on the signal.

16. The system of claim 15 , further comprising:

a cooling plate sensor configured to detect the presence of the wafer on the cooling plate.

17. The system of claim 16 , wherein the cooling plate sensor is further configured to:

provide an indication of a temperature of the cooling plate to the cooling controller.

18. The system of claim 15 , wherein the cooling controller, to determine the cooling time, is configured to:

adjust a default cooling time using the time adjustment.

19. The system of claim 15 , wherein the cooling controller is further configured to:

provide another signal to the cooling plate to cause the cooling plate to stop cooling the wafer.

20. The system of claim 15 , wherein the cooling controller, to determine the time adjustment, is configured to:

determine the time adjustment based on a scaling factor applied to the pattern mask area.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 31, 2023
From: LEE, YUNG-YAO; HU, CHENG-KANG; PENG, JUI-CHUN; LIU, HSU-SHUI
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 064434/0893 →
Continuity (2)
Continuation 17301322 · Mar 31, 2021
Related Publication 20230384776A1 · Nov 30, 2023
References Cited (19)
US 6266125B1 · Fukuda · 2001 [cited by examiner]
US 8376637B2 · Yamada · 2013 [cited by examiner]
US 10712672B2 · Jochemsen · 2020 [cited by examiner]
US 11195744B2 · Fujii · 2021 [cited by examiner]
US 20050177811A1 · Kotani · 2005 [cited by examiner]
US 20050273754A1 · Nojima · 2005 [cited by examiner]
US 20080215276A1 · Fang · 2008 [cited by examiner]
US 20090250826A1 · Inomata · 2009 [cited by examiner]
US 20100036514A1 · Funk · 2010 [cited by examiner]
US 20150316861A1 · Cheng · 2015 [cited by examiner]
US 20160376697A1 · Fujinaga · 2016 [cited by examiner]
US 20170028560A1 · Senn · 2017 [cited by examiner]
US 20180218925A1 · Shigetomi · 2018 [cited by examiner]
US 20190198299A1 · Watanabe · 2019 [cited by examiner]
US 20220034708A1 · Elliott · 2022 [cited by examiner]
US 20220317668A1 · Lee et al. · 2022 [cited by applicant]
JP 2006080410A · 2006 [cited by applicant]
JP 2015102389A · 2015 [cited by applicant]
KR 101647688B1 · 2016 [cited by applicant]