IP Library › Granted Patent US 12,235,785
Granted Patent B2
US 12,235,785 · App. 18/371,128 · Granted Feb 25, 2025

Computer system and a computer device

Inventor: Jonathan Glickman (Needham, MA)
G06F13/4027G06F12/0246G06F13/1694G06F13/28G06F13/4022G06F13/4068G06F13/4282G06F2212/7201
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Quick Facts
Patent No.
US 12,235,785
App. No.
18/371,128
Granted
Feb 25, 2025
Kind
B2
Abstract

A computer system is provided. The computer system includes a hub board, a common bus, and a plurality of Sibling boards. The hub board has an I/O controller hub, which includes a main communication chipset. The plurality of Sibling boards is coupled to the hub board by the common bus. Each of the Sibling boards includes a memory and at least one CPU. The memory is operative to host a Sibling operating system. The CPU is coupled to the memory. The Southbridge type chipset which resides in the hub board is shared amongst the plurality of Sibling boards. At least one of the plurality of Sibling boards functions as a master processing unit of the system. Sibling boards offer processing flexibility through the means of how they are configured in the system.

Claims (30)

1. A computer system comprising:

a first board having an I/O controller hub including a main communication chipset;

a common bus; and

a plurality of Sibling boards coupled to said first board by said common bus, each of the Sibling boards comprising,

a memory operative to host a Sibling operating system, and

at least one graphics processing unit (GPU) coupled to said memory, said Sibling board configured without a Sibling chipset;

wherein at least one of the plurality of Sibling boards functions as a processing unit of said first board, and at least one of said Sibling boards is coupled to and shares said I/O controller hub.

2. The computer system of claim 1 , wherein said I/O controller hub includes a main network device; and wherein at least one of said Sibling boards is coupled to and shares said main network device.

3. The computer system of claim 2 , wherein at least one of said Sibling boards is directly coupled to and shares said main network device, and is without an external I/O circuit.

4. The computer system of claim 1 , wherein said common bus physically and electrically connects the plurality of said Sibling boards to said first board.

5. The computer system of claim 1 , wherein said common bus couples the plurality of said Sibling boards to said first board.

6. The computer system of claim 1 , wherein each of said Sibling boards includes at least one solid state memory drive.

7. The computer system of claim 6 , wherein each of said Sibling boards includes a conventional hard disk drive, and has a RAID 0 setup with said solid state drive and said conventional hard disk drive.

8. The computer system of claim 1 , wherein one of said Sibling boards hosts a first Sibling operating system and another of said Sibling boards hosts a second Sibling operating system that is different from said first Sibling operating system.

9. The computer system of claim 1 , wherein one of said Sibling boards and another of said Sibling boards host a same Sibling operating system.

10. The computer system of claim 1 , wherein at least one of said Sibling boards is a master node and another one of said Sibling boards is a slave node.

11. The computer system of claim 1 , wherein said common bus is comprised of at least one of a PLX technology PCie (Peripheral Component Interconnect Express) and Fiber Fabric Hub technologies.

12. The computer system of claim 1 , wherein said common bus connects one of said Sibling boards to another of said Sibling boards in a series or parallel arrangement.

13. The computer system of claim 1 , wherein each of said Sibling boards includes a first disk controller that is configured to be accessed by said common bus or to connect with said memory.

14. The computer system of claim 13 , wherein each of said Sibling boards further comprises a second disk controller that resides on said Sibling board and is configured to connect to an external storage device.

15. The computer system of claim 1 , wherein said first board is without a processing unit.

16. The computer system of claim 1 , wherein said computer system is virtualized to provide said first board for I/O controller hub sharing, and provide said plurality of Sibling boards for data processing.

17. The computer system of claim 1 , wherein a specific function is assigned to each of said Sibling boards such that when said I/O controller hub receives a request for a specific function from a server, said Sibling boards to which that specific function is assigned is connected to said server.

18. A computer device comprising

a first board having an I/O controller hub,

a plurality of Sibling boards stacked together, each of the Sibling boards coupled to said first board, each of said Sibling boards being operative to host a Sibling operating system and comprises a graphics processing unit (GPU) connected to a memory; and

a common bus connecting the plurality of said Sibling boards to said first board;

wherein at least one of the plurality of said Sibling boards functions as a processing unit for said first board, and the at least one of said Sibling boards is coupled to and shares said I/O controller hub.

19. The computer system of claim 18 , wherein said I/O controller hub includes a main network device; and wherein at least one of said Sibling boards is coupled to and shares said main network device.

20. The computer system of claim 19 , wherein at least one of said Sibling boards is directly coupled to and shares said main network device, and is without an external I/O circuit.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 14, 2026
From: GLICKMAN, JONATHAN
To: JMG VENTURES LLC
Reel/Frame 074656/0897 →
Continuity (8)
Continuation 17018808 · Sep 11, 2020
Continuation 16009687 · Jun 15, 2018
Continuation 15696747 · Sep 6, 2017
Continuation 15293459 · Oct 14, 2016
Continuation 14853271 · Sep 14, 2015
Continuation 14244744 · Apr 3, 2014
Provisional Application 61818412 · May 1, 2013
Related Publication 20240012777A1 · Jan 11, 2024
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