Granted Patent B2

US 12,652,790 · App. 18/374,154 · Granted Jun 9, 2026

Inventor: Tse-Yao Huang (Taipei City, TW)

Assignee: NANYA TECHNOLOGY CORPORATION

H10B12/09H10B12/34H10B12/50

Abstract

Claims (29)

1 . A semiconductor device, comprising:

a substrate comprising an array area and a peripheral area;

a peripheral gate structure comprising:

a peripheral gate dielectric layer inwardly positioned in the peripheral area of the substrate and comprising a U-shaped cross-sectional profile;

a peripheral gate conductor comprising a bottom portion positioned on the peripheral gate dielectric layer and a neck portion positioned on the bottom portion; and

a peripheral gate capping layer positioned on the peripheral gate dielectric layer and the bottom portion, and surrounding the neck portion; and

an array gate structure positioned in the array area of the substrate;

wherein a top surface of the peripheral gate capping layer and a top surface of the neck portion are substantially coplanar;

wherein a width of the peripheral gate structure is greater than a width of the array gate structure;

wherein the peripheral gate structure comprises a top portion positioned on the neck portion, and a width of the top portion and a width of the neck portion are substantially the same;

wherein the array gate structure comprising:

an array gate dielectric layer inwardly positioned in the array area of the substrate;

an array gate conductor positioned on the array gate dielectric layer; and

an array gate capping layer positioned on the array gate conductor;

wherein the peripheral gate dielectric layer and the array gate dielectric layer comprise different materials.

2 . The semiconductor device of claim 1 , wherein the peripheral gate conductor and the array gate conductor comprise different materials.

3 . The semiconductor device of claim 2 , further comprising a peripheral impurity region positioned in the peripheral area of the substrate and adjacent to the peripheral gate capping layer.

4 . The semiconductor device of claim 3 , wherein a bottom surface of the peripheral impurity region is at a vertical level lower than a bottom surface of the peripheral gate capping layer.

5 . A semiconductor device, comprising:

a substrate comprising an array area and a peripheral area;

a peripheral gate structure comprising:

a peripheral gate dielectric layer inwardly positioned in the peripheral area of the substrate and comprising a U-shaped cross-sectional profile;

a peripheral gate conductor comprising a bottom portion positioned on the peripheral gate dielectric layer and a neck portion positioned on the bottom portion; and

a peripheral gate capping layer positioned on the peripheral gate dielectric layer and the bottom portion, and surrounding the neck portion; and

an array gate structure positioned in the array area of the substrate;

wherein a top surface of the peripheral gate capping layer and a top surface of the neck portion are substantially coplanar;

wherein a width of the peripheral gate structure is greater than a width of the array gate structure;

wherein the peripheral gate structure comprises a top portion positioned on the neck portion, and a width of the top portion and a width of the neck portion are substantially the same;

wherein a bottom surface of the peripheral gate structure is at a vertical level lower than a bottom surface of the array gate structure.

Assignments (1)

Continuity (2)

References Cited (14)