Selective recessing to form a fully aligned via
A method of forming a semiconductor device having a vertical metal line interconnect (via) fully aligned to a first direction of a first interconnect layer and a second direction of a second interconnect layer in a selective recess region by forming a plurality of metal lines in a first dielectric layer; and recessing in a recess region first portions of the plurality of metal lines such that top surfaces of the first portions of the plurality of metal lines are below a top surface of the first dielectric layer; wherein a non-recess region includes second portions of the plurality of metal lines that are outside the recess region.
1. A device comprising:
an interconnect structure comprising first and second metal lines formed in a first dielectric layer, wherein:
the second metal line extends parallel to the first metal line in a first direction;
the second metal line is disposed adjacent to the first metal line;
a first region comprises a first segment of the first metal line and an adjacent first segment of the second metal line;
a second region comprises a second segment of the first metal line and an adjacent second segment of the second metal line;
the second region is adjacent to the first region; and
a top surface of the first segment of the first metal line and a top surface of the first segment of the second metal line are recessed relative to a top surface of the first dielectric layer and relative to a top surface of the second segment of the first metal line and a top surface of the second segment of the second metal line.
2. The device of claim 1 , wherein:
the first region is disposed between a third region and the second region, and the third region comprises a third segment of the first metal line and an adjacent third segment of the second metal line; and
the top surface of the second segment of the first metal line and the top surface of the second segment of the second metal line are substantially coplanar with a top surface of the third segment of the first metal line and a top surface of the third segment of the second metal line.
3. The device of claim 1 , further comprising a third metal line which (i) is formed in the first dielectric layer, (ii) extends in the first direction parallel to the first metal line and the second metal line, wherein:
the first metal line is disposed between the third metal line and the second metal line,
the first metal line is disposed adjacent to the third metal line and the second metal line,
the first region comprises a first segment of the third metal line; and
a top surface of the first segment of the third metal line is substantially coplanar with the top surface of the first segment of the first metal line and the top surface of the first segment of the second metal line.
4. The device of claim 1 , further comprising a third metal line which (i) is formed in the first dielectric layer, (ii) extends in the first direction parallel to the first metal line and the second metal line, wherein:
the second metal line is disposed between the third metal line and the first metal line,
the second metal line is disposed adjacent to the third metal line and the first metal line
the third metal line is disposed in a third region adjacent to the first and second regions,
the third metal line comprises a first segment adjacent to the first segment of the second metal line and a second segment adjacent to the second segment of the second metal line, and a top surface of the first segment of the third metal line is substantially coplanar with a top surface of the second segment of the third metal line and the top surface of the second segment of the second metal line.
5. The device of claim 1 , further comprising:
an interlayer dielectric layer disposed on the first dielectric layer; and
a via through the interlayer dielectric layer connected to the first segment of the first metal line.
6. The device of claim 5 , wherein:
the interlayer dielectric layer comprises (i) a cap layer and (ii) a second dielectric layer disposed on the cap layer;
the cap layer comprises one or more first materials;
the second dielectric layer comprises one or more second materials; and
at least one of the one or more first materials is different from at least one of the one or more second materials.
7. The device of claim 6 , wherein the cap layer comprises silicon and nitrogen.
8. The device of claim 6 , wherein the cap layer comprises silicon, nitrogen, and carbon.
9. The device of claim 6 , wherein the cap layer comprises a metal oxide.
10. The device of claim 2 , further comprising:
an interlayer dielectric layer disposed on the first dielectric layer; and
a via through the interlayer dielectric layer connected to the first segment of the first metal line.
11. The device of claim 3 , further comprising:
an interlayer dielectric layer disposed on the first dielectric layer; and
a via through the interlayer dielectric layer connected to the first segment of the first metal line.
12. The device of claim 4 , further comprising:
an interlayer dielectric layer disposed on the first dielectric layer; and
a via through the interlayer dielectric layer connected to the first segment of the first metal line.
13. A device comprising:
an interconnect structure comprising first, second, and third metal lines formed in a first dielectric layer, wherein:
the second and third metal lines extends parallel to the first metal line in a first direction;
the first metal line is disposed (i) adjacent to the second metal line and the third metal line and (ii) between the second metal line and the third metal line;
a first region comprises a first segment of the first metal line, a first segment of the second metal line and a first segment of the third metal line;
a second region comprises a second segment of the first metal line, a second segment of the second metal line and a second segment of the third metal line; and
a top surface of the first segment of the first metal line, a top surface of the first segment of the second metal line and a top surface of the first segment of the third metal line are recessed relative to a top surface of the first dielectric layer, relative to a top surface of the second segment of the first metal line, a top surface of the second segment of the second metal line, and a top surface of the second segment of the third metal line.
14. The device of claim 13 , wherein:
the first region is disposed between a third region and the second region, and the third region comprises adjacent third segments of the first, second, and third metal lines; and
the top surface of the first segment of the first metal line, the top surface of the first segment of the second metal line and the top surface of the first segment of the third metal line are recessed relative to a top surface of the third segment of the first metal line, a top surface of the third segment of the second metal line and a top surface of the third segment of the third metal line.
15. The device of claim 13 , comprising a fourth metal line which (i) is formed in the first dielectric layer, (ii) extends in the first direction parallel to the first metal line, the second metal line and the third metal line, wherein:
the second metal line is disposed between and adjacent to the first metal line and the fourth metal line,
a fourth region comprises first and second segments of the fourth metal line, adjacent to the first and second segments of the second metal line, respectively; and
a top surface of the first segment of the fourth metal line is substantially coplanar with a top surface of the second segment of the fourth metal line and with the top surface of the second segment of the second metal line.
16. The device of claim 15 , further comprising:
an interlayer dielectric layer disposed on (i) the first dielectric layer, (ii) the first metal line, (iii) the second metal line, (iv) the third metal line, and (v) the fourth metal line; and
a via through the interlayer dielectric layer connecting to the first segment of the first metal line.
17. The device of claim 13 , further comprising:
an interlayer dielectric layer disposed on (i) the first dielectric layer, (ii) the first metal line, (iii) the second metal line, and (iv) the third metal line; and
a via through the interlayer dielectric layer connecting to the first segment of the first metal line.
18. The device of claim 14 , further comprising:
an interlayer dielectric layer disposed on (i) the first dielectric layer, (ii) the first metal line, (iii) the second metal line, and (iv) the third metal line; and
a via through the interlayer dielectric layer connecting to the first segment of the first metal line.
19. The device of claim 16 , wherein:
the interlayer dielectric layer comprises (i) a cap layer and (ii) a second dielectric layer disposed on the cap layer;
the cap layer comprises one or more first materials;
the second dielectric layer comprises one or more second materials; and
at least one of the one or more first materials is different from at least one of the one or more second materials.
20. The device of claim 19 , wherein the cap layer comprises silicon and nitrogen.
21. The device of claim 19 , wherein the cap layer comprises silicon, nitrogen, and carbon.
22. The device of claim 19 , wherein the cap layer comprises a metal oxide.