IP Library › Granted Patent US 12,339,723
Granted Patent B2
US 12,339,723 · App. 18/384,180 · Granted Jun 24, 2025

Controlling operating voltage of a processor

Inventors: Ryan D. Wells (Folsom, CA); Itai Feit (Herzeliya, IL); Doron Rajwan (Rishon Le-Zion, IL); Nadav Shulman (Tel Mond, IL); Zeev Offen (Folsom, CA); Inder M. Sodhi (Folsom, CA)
Assignee: Daedalus Prime LLC
G06F1/28G06F1/266G06F1/3206G06F1/324G06F1/26G06F1/3296G06F12/0811G06F12/0815G06F12/0897Y02D10/00
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Quick Facts
Patent No.
US 12,339,723
App. No.
18/384,180
Granted
Jun 24, 2025
Kind
B2
Abstract

In an embodiment, a processor includes a core domain with a plurality of cores and a power controller having a first logic to receive a first request to increase an operating voltage of a first core of the core domain to a second voltage, to instruct a voltage regulator to increase the operating voltage to an interim voltage, and to thereafter instruct the voltage regulator to increase the operating voltage to the second voltage. Other embodiments are described and claimed.

Claims (15)

1. A multicore processor comprising:

a plurality of cores, wherein each core comprises a processor configured to operate at an independent voltage and frequency level and at least one core of the plurality of cores is coupled to a plurality of levels of cache memory; and

a power control unit coupled to each of the plurality of cores and, responsive to receiving a first request to alter an operating state of a first core of the plurality of cores from a current operating state to a modified operating state, configured to cause an operating frequency and voltage to be updated for the first core by, prior to modifying a frequency level of the first core from a first frequency level associated with the current operating state to a second frequency level associated with the modified operating state, modifying a voltage for the multicore processor from a current voltage to an intermediate voltage that is a voltage sufficient to power up a second core of the plurality of cores from a low power state to an active state, and, after modification of the voltage for the multicore processor to the intermediate voltage has been achieved, modifying the voltage for the multicore processor from the intermediate voltage to a voltage appropriate for operating the first core at the second frequency level associated with the modified operating state and thereafter changing the operating frequency of the first core from the first frequency level to the second frequency level.

2. The multicore processor of claim 1 wherein, each core of the plurality of cores is coupled to a coherent fabric to provide a cache coherent interconnection.

3. The multicore processor of claim 1 wherein each core of the plurality of cores is configured to operate at a plurality of performance levels.

4. The multicore processor of claim 1 wherein the first frequency level places the first core in an inactive state.

5. The multicore processor of claim 1 wherein the cache memory comprises a shared memory comprising a plurality of units of a last level cache (LLC).

6. The multicore processor of claim 2 where each core of the plurality of cores is configured to operate at a plurality of performance levels.

7. The multicore processor of claim 6 wherein the first frequency level places the first core in an inactive state.

8. The multicore processor of claim 7 wherein the cache memory comprises a shared memory comprising a plurality of units of a last level cache (LLC).

9. The multicore processor of claim 1 wherein the power control unit is located in an uncore.

10. The multicore processor of claim 9 wherein the uncore further comprises frequency control logic.

11. The multicore processor of claim 10 , wherein the second frequency level is an operating frequency level.

12. The multicore processor of claim 1 wherein the power control unit is configured be independent of and complementary to an operating system (OS)-based mechanism.

13. The multicore processor of claim 1 wherein a core of the plurality of cores operating at the third second frequency level operates at a higher frequency than the first frequency level.

Continuity (8)
Continuation 17969408 · Nov 1, 2022
Continuation 17645202 · Dec 20, 2021
Continuation 17501580 · Oct 14, 2021
Continuation 16527150 · Jul 31, 2019
Continuation 15966397 · Apr 30, 2018
Continuation 15157553 · May 18, 2016
Continuation 13793037 · Mar 11, 2013
Related Publication 20240192751A1 · Jun 13, 2024
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