Bootstrap circuit and communication device including the same
A bootstrap circuit for generating an output signal through a pre-charge operation and a sample operation, includes: a sampler including a sampling switch configured to sample an input signal, a first protection switch connected between an input node and the sampling switch, and a second protection switch connected between the sampling switch and an output node; and a driver configured to drive the sampler based on a power supply voltage and the input signal.
1 . A bootstrap circuit for generating an output signal through a pre-charge operation and a sample operation, the bootstrap circuit comprising:
a sampler comprising:
a sampling switch configured to sample an input signal,
a first protection switch connected between an input node and the sampling switch, and
a second protection switch connected between the sampling switch and an output node; and
a driver configured to drive the sampler based on a power supply voltage and the input signal,
wherein the bootstrap circuit further comprises a first capacitor and a level shifter configured to control a first voltage based on the power supply voltage and the input signal,
wherein the level shifter comprises a second capacitor,
wherein the driver comprises:
a first p-channel metal-oxide semiconductor (PMOS) transistor comprising:
a source,
a body, and
a drain connected to a power supply terminal;
a second PMOS transistor comprising:
a source,
a body connected to the body of the first PMOS transistor, and
a drain connected to the source of the first PMOS transistor,
a bootstrap capacitor comprising:
one end connected to the source of the second PMOS transistor, and
another end;
a first n-channel metal-oxide semiconductor (NMOS) transistor comprising a drain connected to the other end of the bootstrap capacitor; and
a second NMOS transistor comprising a drain connected to the source of the first NMOS transistor and a source connected to a ground terminal, and
wherein the first capacitor is the bootstrap capacitor.
2 . The bootstrap circuit of claim 1 , wherein the bootstrap capacitor is configured to be charged by turning on the first PMOS transistor, the second PMOS transistor, the first NMOS transistor, and the second NMOS transistor during the pre-charge operation.
3 . The bootstrap circuit of claim 1 , wherein the driver is configured to turn on the first protection switch and the second protection switch by applying the power supply voltage to a gate of the first protection switch and a gate of the second protection switch during the pre-charge operation.
4 . The bootstrap circuit of claim 1 , wherein the driver is configured to turn off the sampling switch by applying a ground voltage to a gate of the sampling switch during the pre-charge operation.
5 . The bootstrap circuit of claim 1 , wherein the bootstrap capacitor is configured to be discharged when the second PMOS transistor and the second NMOS transistor are turned off during the sample operation.
6 . The bootstrap circuit of claim 1 , wherein the driver is configured to turn on the sampling switch by applying a voltage to a gate of the sampling switch during the sample operation, and
wherein the voltage is obtained by adding the power supply voltage to the voltage of the input signal.
7 . The bootstrap circuit of claim 1 , wherein the driver further comprises:
a third NMOS transistor comprising:
a source connected to the other end of the bootstrap capacitor,
a drain, and
a gate connected to the source of the second PMOS transistor;
a fourth NMOS transistor comprising:
a source connected to the drain of the third NMOS transistor,
a drain, and
a gate connected to the gate of the second PMOS transistor; and
a fifth NMOS transistor comprising:
a source connected to the drain of the fourth NMOS transistor,
a gate connected to the source of the second PMOS transistor, and
a drain connected to the input node.
8 . The bootstrap circuit of claim 1 , wherein the driver further comprises:
a third PMOS transistor comprising:
a source,
a gate,
a drain, and
a body connected to the source of the second PMOS transistor; and
a fourth PMOS transistor comprising:
a source connected to the drain of the third PMOS transistor,
a body connected to the body of the third PMOS transistor,
a gate connected to the other end of the bootstrap capacitor, and
a drain connected to the gate of the sampling switch.
9 . The bootstrap circuit of claim 8 , wherein the first voltage is applied to the gate of the third PMOS transistor.
10 . The bootstrap circuit of claim 1 , wherein the driver comprises:
a first NMOS transistor comprising:
a drain, and
a source connected to a gate of the sampling switch;
a second NMOS transistor comprising:
a drain, and
a source connected to the drain of the first NMOS transistor; and
a third NMOS transistor comprising a source connected to the drain of the second NMOS transistor and a drain connected to a ground terminal.
11 . A bootstrap circuit comprising:
a sampler comprising:
a sampling switch configured to sample an input signal,
a first protection switch connected between an input node and the sampling switch, and
a second protection switch connected between the sampling switch and an output node; and
a driver configured to drive the sampler by adjusting a voltage applied to the sampler based on a logic level of a control signal,
wherein the bootstrap circuit further comprises a first capacitor and a level shifter configured to control a first voltage based on a power supply voltage and the input signal, and
wherein the level shifter comprises a second capacitor,
wherein the driver comprises:
a first p-channel metal-oxide semiconductor (PMOS) transistor comprising:
a source,
a body, and
a drain connected to a power supply terminal;
a second PMOS transistor comprising:
a source,
a body connected to the body of the first PMOS transistor, and
a drain connected to the source of the first PMOS transistor,
a bootstrap capacitor comprising:
one end connected to the source of the second PMOS transistor, and
another end;
a first n-channel metal-oxide semiconductor (NMOS) transistor comprising a drain connected to the other end of the bootstrap capacitor; and
a second NMOS transistor comprising a drain connected to the source of the first NMOS transistor and a source connected to a ground terminal, and
wherein the first capacitor is the bootstrap capacitor.
12 . The bootstrap circuit of claim 11 , wherein the bootstrap capacitor is provided between the power supply terminal and the ground terminal,
wherein, based on the control signal that is at a high logic level, one end of the bootstrap capacitor is connected to the power supply terminal and the other end of the bootstrap capacitor is connected to the ground terminal to charge the bootstrap capacitor.
13 . The bootstrap circuit of claim 11 , wherein, based on the control signal that is a high logic level, the driver is configured to turn on the first protection switch and the second protection switch by applying the power supply voltage to a gate of the first protection switch and a gate of the second protection switch.
14 . The bootstrap circuit of claim 11 , wherein, based on the control signal that is a high logic level, the driver is configured to turn off the sampling switch by applying a ground voltage to a gate of the sampling switch.
15 . A communication device comprising:
a bootstrap circuit; and
a control circuit configured to generate a control signal,
wherein the bootstrap circuit comprises:
a sampler comprising:
a sampling switch configured to sample an input signal,
a first protection switch connected between an input node and the sampling switch, and
a second protection switch connected between the sampling switch and an output node; and
a driver configured to drive the sampler based on the control signal,
wherein the bootstrap circuit further comprises and a first capacitor a level shifter configured to control a first voltage based on a power supply voltage and the input signal, and
wherein the level shifter comprises a second capacitor,
wherein the driver comprises:
a first p-channel metal-oxide semiconductor (PMOS) transistor comprising:
a source,
a body, and
a drain connected to a power supply terminal;
a second PMOS transistor comprising:
a source,
a drain connected to the source of the first PMOS transistor, and
a body connected to the body of the first PMOS transistor;
a bootstrap capacitor comprising one end connected to the source of the second PMOS transistor;
a first n-channel metal-oxide semiconductor (NMOS) transistor comprising a drain connected to another end of the bootstrap capacitor; and
a second NMOS transistor comprising a drain connected to the source of the first NMOS transistor and a source connected to a ground terminal, and
wherein the first capacitor is the bootstrap capacitor.
16 . The communication device of claim 15 , wherein the driver comprises:
a third PMOS transistor comprising:
a drain,
a gate,
a source, and
a body connected to the source of the second PMOS transistor; and
a fourth PMOS transistor comprising:
a source connected to the drain of the third PMOS transistor,
a body connected to the body of the third PMOS transistor,
a gate connected to the other end of the bootstrap capacitor, and
a drain connected to a gate of the sampling switch.