Parallel processing using hazard detection and mitigation
Techniques for parallel processing using hazard detection and mitigation are disclosed. An array of compute elements is accessed. Each compute element within the array of compute elements is known to a compiler and is coupled to its neighboring compute elements within the array of compute elements. Control for the compute elements is provided on a cycle-by-cycle basis. Control is enabled by a stream of wide control words generated by the compiler. Memory access operations are tagged with precedence information. The tagging is contained in the control words. The tagging is provided by the compiler at compile time. Memory access operations are monitored. The monitoring is based on the precedence information and a number of architectural cycles of the cycle-by-cycle basis. The tagging is augmented at run time, based on the monitoring. Memory access data is held before promotion, based on the monitoring.
1 . A processor-implemented method for parallel processing comprising:
accessing an array of compute elements, wherein each compute element within the array of compute elements is known to a compiler and is coupled to its neighboring compute elements within the array of compute elements, wherein each compute element is disposed within one or more integrated circuits;
providing control for the compute elements on a cycle-by-cycle basis, wherein the control is enabled by a stream of control words generated by the compiler;
tagging memory access operations with precedence information, wherein the tagging is contained in the control words, wherein the tagging includes tagging store accesses with a unique precedence tag, wherein the unique precedence tag is based on a cycle count that includes a number of cycles within which a store access must occur before an out-of-time exception is thrown, and wherein the tagging is provided by the compiler at compile time;
monitoring the memory access operations, wherein the monitoring is based on the precedence information and a number of architectural cycles of the cycle-by-cycle basis; and
holding memory access data before promotion, based on the monitoring.
2 . The method of claim 1 further comprising augmenting the tagging at run time, based on the monitoring.
3 . The method of claim 1 wherein the holding is accomplished using access buffers coupled to a memory cache.
4 . The method of claim 3 wherein the holding prevents premature data promotion into or out of the memory cache.
5 . The method of claim 3 wherein the memory cache comprises a data cache for the array of compute elements.
6 . The method of claim 3 wherein the memory cache has an access time that is unknown to the compiler.
7 . The method of claim 3 further comprising transferring the memory access data between the array of compute elements and the access buffers using a crossbar switch.
8 . The method of claim 7 wherein a delay for the transferring is unknown to the compiler.
9 . The method of claim 7 wherein the unique precedence tag enables load access priority in the crossbar switch.
10 . The method of claim 1 wherein the precedence information enables hardware ordering of memory access loads to the array of compute elements and memory access stores from the array of compute elements.
11 . The method of claim 10 wherein the precedence information provides semantically correct operation ordering.
12 . The method of claim 1 wherein the precedence information comprises intra-control word precedence and inter-control word precedence.
13 . The method of claim 1 further comprising identifying hazardous loads and stores by comparing load and store addresses to contents of an access buffer.
14 . The method of claim 13 wherein the comparing identifies potential accesses to a same address.
15 . The method of claim 13 further comprising including the precedence information in the comparing.
16 . The method of claim 13 further comprising delaying promoting of data to the access buffer and releasing of the data from the access buffer.
17 . The method of claim 16 wherein the delaying avoids hazards.
18 . The method of claim 17 wherein the avoiding the hazards is based on a comparative precedence value.
19 . The method of claim 17 wherein the hazards include write-after-read conflicts, read-after-write conflicts, and write-after-write conflicts.
20 . The method of claim 13 wherein the identifying enables hazard mitigation.
21 . The method of claim 20 wherein the hazard mitigation includes load-to-store forwarding, store-to-load forwarding, and store-to-store forwarding.
22 . The method of claim 1 wherein the control words include branch operations.
23 . The method of claim 22 further comprising suppressing memory access stores for untaken branch paths.
24 . A computer program product embodied in a non-transitory computer readable medium for parallel processing, the computer program product comprising code which causes one or more processors to perform operations of:
accessing an array of compute elements, wherein each compute element within the array of compute elements is known to a compiler and is coupled to its neighboring compute elements within the array of compute elements, wherein each compute element is disposed within one or more integrated circuits;
providing control for the compute elements on a cycle-by-cycle basis, wherein the control is enabled by a stream of control words generated by the compiler;
tagging memory access operations with precedence information, wherein the tagging is contained in the control words, wherein the tagging includes tagging store accesses with a unique precedence tag, wherein the unique precedence tag is based on a cycle count that includes a number of cycles within which a store access must occur before an out-of-time exception is thrown, and wherein the tagging is provided by the compiler at compile time;
monitoring the memory access operations, wherein the monitoring is based on the precedence information and a number of architectural cycles of the cycle-by-cycle basis; and
holding memory access data before promotion, based on the monitoring.
25 . A computer system for parallel processing comprising:
a memory which stores instructions;
one or more processors coupled to the memory, wherein the one or more processors, when executing the instructions which are stored, are configured to:
access an array of compute elements, wherein each compute element within the array of compute elements is known to a compiler and is coupled to its neighboring compute elements within the array of compute elements, wherein each compute element is disposed within one or more integrated circuits;
provide control for the compute elements on a cycle-by-cycle basis, wherein the control is enabled by a stream of control words generated by the compiler;
tag memory access operations with precedence information, wherein the tagging is contained in the control words, wherein the tagging includes tagging store accesses with a unique precedence tag, wherein the unique precedence tag is based on a cycle count that includes a number of cycles within which a store access must occur before an out-of-time exception is thrown, and wherein the tagging is provided by the compiler at compile time;
monitor the memory access operations, wherein the monitoring is based on the precedence information and a number of architectural cycles of the cycle-by-cycle basis; and
hold memory access data before promotion, based on the monitoring.