Granted Patent B2

US 12,353,608 · App. 18/392,055 · Granted Jul 8, 2025

Inventors: Uday Savagaonkar (Redmond, WA); Eric Northup (Seattle, WA)

Assignee: Google LLC

G06F21/72G06F13/4221G06F21/602G06F21/79G06F2213/0026

Abstract

Claims (46)

1. A system for providing a secure collaboration between one or more hardware accelerators and an enclave defined within memory of a host computing device, the system comprising an accelerator apparatus configured to:

negotiate a cryptographic session between the one or more hardware accelerators and the enclave using a cryptographic hardware identity provided by a microcontroller; and

during the cryptographic session:

retrieve encrypted information from the enclave;

decrypt the encrypted information using a cryptographic engine that is separate from the one or more hardware accelerators;

retrieve unencrypted information;

process the unencrypted information to generate results;

encrypt the results using the cryptographic engine; and

send the encrypted results back to the enclave.

2. The system of claim 1 , wherein the one or more hardware accelerators comprise at least one of a tensor processing unit or a graphics processing unit.

3. The system of claim 1 , wherein the accelerator apparatus is further configured to manage keys used by the cryptographic engine for the encryption and decryption operations using an application processor.

4. The system of claim 1 , wherein the accelerator apparatus is further configured to manage the cryptographic hardware identity using an application processor.

5. The system of claim 1 , wherein the cryptographic engine is configured to decrypt information leaving the enclave during the cryptographic session.

6. The system of claim 1 , wherein the cryptographic engine is configured to encrypt information entering the enclave during the cryptographic session.

7. The system of claim 1 , wherein the cryptographic engine is a line-rate cryptographic engine.

8. The system of claim 1 , wherein the cryptographic engine is arranged between the one or more hardware accelerators and the enclave.

9. The system of claim 1 , wherein the accelerator apparatus is further configured to generate certificate signing requests (CSRs) to secure the cryptographic hardware identity using the microcontroller.

10. A method for providing a secure collaboration between one or more hardware accelerators and an enclave defined within memory of a host computing device, the method comprising:

negotiating, by one or more processors, a cryptographic session between the one or more hardware accelerators and the enclave using a cryptographic hardware identity provided by a microcontroller; and

during the cryptographic session:

retrieving, by the one or more processors, encrypted information from the enclave;

decrypting, by the one or more processors, the encrypted information using a cryptographic engine that is separate from the one or more hardware accelerators;

retrieving, by the one or more processors, unencrypted information;

processing, by the one or more processors, the unencrypted information to generate results;

encrypting, by the one or more processors, the results using the cryptographic engine; and

sending, by the one or more processors, the encrypted results back to the enclave.

11. The method of claim 10 , wherein the one or more hardware accelerators comprise at least one of a tensor processing unit or a graphics processing unit.

12. The method of claim 10 , further comprising managing, by the one or more processors, keys used by the cryptographic engine for the encryption and decryption operations using an application processor.

13. The method of claim 10 , further comprising managing, by the one or more processors, the cryptographic hardware identity using an application processor.

14. The method of claim 10 , wherein the cryptographic engine is a line-rate cryptographic engine.

15. The method of claim 10 , wherein the cryptographic engine is arranged between the one or more hardware accelerators and the enclave.

16. The method of claim 10 , further comprising generating, by the one or more processors, certificate signing request (CSRs) to secure the cryptographic hardware identity using the microcontroller.

17. A non-transitory computer-readable medium storing instructions executable by one or more processors for providing a secure collaboration between one or more hardware accelerators and an enclave defined within memory of a host computing device, the instructions comprising:

negotiating a cryptographic session between the one or more hardware accelerators and the enclave using a cryptographic hardware identity provided by a microcontroller; and

during the cryptographic session:

retrieving encrypted information from the enclave;

decrypting the encrypted information using a cryptographic engine that is separate from the one or more hardware accelerators;

retrieving unencrypted information;

processing the unencrypted information to generate results;

encrypting the results using the cryptographic engine; and

sending the encrypted results back to the enclave.

18. The non-transitory computer-readable medium of claim 17 , wherein the one or more hardware accelerators comprise at least one of a tensor processing unit or a graphics processing unit.

19. The non-transitory computer-readable medium of claim 17 , wherein the instructions further comprise:

managing keys used by the cryptographic engine for the encryption and decryption operations using an application processor; and

managing the cryptographic hardware identity using the application processor.

20. The non-transitory computer-readable medium of claim 17 , wherein the instructions further comprise generating certificate signing request (CSRs) to secure the cryptographic hardware identity using the microcontroller.

Assignments (1)

Continuity (4)

References Cited (291)