Semiconductor device, semiconductor device control method, and semiconductor device manufacturing method to increase allowable range of transition time difference between two signals
A semiconductor device includes: a semiconductor substrate; a first semiconductor layer and a second semiconductor layer located in a surface layer of the semiconductor substrate to be excluded from each other; a third semiconductor layer located on an opposite side of the first semiconductor layer and the second semiconductor layer from the semiconductor substrate; a fourth semiconductor layer and a fifth semiconductor layer located on an opposite side of the third semiconductor layer from the semiconductor substrate to be excluded from each other; and a first electrode, a second electrode, and a third electrode each having an insulating surface, and the first electrode extends through the fifth semiconductor layer, and the third semiconductor layer to reach the first semiconductor layer.
1 . A semiconductor device comprising:
a semiconductor substrate of a first conductivity type;
a first semiconductor layer of the first conductivity type located in a surface layer of the semiconductor substrate;
a second semiconductor layer of the first conductivity type located in the surface layer of the semiconductor substrate to be excluded from the first semiconductor layer, the second semiconductor layer having a higher peak impurity concentration than the semiconductor substrate;
a third semiconductor layer of a second conductivity type located on an opposite side of the first semiconductor layer and the second semiconductor layer from the semiconductor substrate;
a fourth semiconductor layer of the second conductivity type selectively located on an opposite side of the third semiconductor layer from the semiconductor substrate, the fourth semiconductor layer having a higher peak impurity concentration than the third semiconductor layer;
a fifth semiconductor layer of the first conductivity type located on an opposite side of the third semiconductor layer from the semiconductor substrate to be excluded from the fourth semiconductor layer, the fifth semiconductor layer having a higher peak impurity concentration than the second semiconductor layer;
a sixth semiconductor layer of the second conductivity type located on an opposite side of the semiconductor substrate from the first semiconductor layer, the second semiconductor layer, the third semiconductor layer, the fourth semiconductor layer, and the fifth semiconductor layer;
a first electrode extending through the fifth semiconductor layer and the third semiconductor layer to reach the first semiconductor layer at a position farther from the sixth semiconductor layer than a boundary between the second semiconductor layer and the semiconductor substrate is, the first electrode having an insulating surface;
a second electrode extending through the second semiconductor layer, the fourth semiconductor layer, and the third semiconductor layer or through the second semiconductor layer, the fifth semiconductor layer, and the third semiconductor layer, to reach the semiconductor substrate, the second electrode being closer to the sixth semiconductor layer than the first semiconductor layer and the second semiconductor layer are, the second electrode having an insulating surface; and
a third electrode extending through the fourth semiconductor layer and the third semiconductor layer to reach the semiconductor substrate, the third electrode being closer to the sixth semiconductor layer than the first semiconductor layer and the second semiconductor layer are, the third electrode separating the first semiconductor layer from the second semiconductor layer, the third electrode and the second electrode sandwiching the second semiconductor layer, the third electrode having an insulating surface.
2 . The semiconductor device according to claim 1 , wherein
the first semiconductor layer has a higher peak impurity concentration than the semiconductor substrate.
3 . The semiconductor device according to claim 2 , wherein
the second electrode extends through the fifth semiconductor layer and the third semiconductor layer.
4 . The semiconductor device according to claim 3 , wherein
the first semiconductor layer has a lower peak impurity concentration than the second semiconductor layer.
5 . The semiconductor device according to claim 4 , wherein
the first semiconductor layer is thinner than the second semiconductor layer.
6 . The semiconductor device according to claim 2 , wherein
the second electrode extends through the fourth semiconductor layer and the third semiconductor layer.
7 . The semiconductor device according to claim 1 , wherein
the first semiconductor layer is a portion of the semiconductor substrate.
8 . The semiconductor device according to claim 1 , wherein
the second electrode extends through the fifth semiconductor layer and the third semiconductor layer.
9 . The semiconductor device according to claim 1 , wherein
the second electrode extends through the fourth semiconductor layer and the third semiconductor layer.
10 . The semiconductor device according to claim 1 , wherein
a length by which the second electrode protrudes from the second semiconductor layer to the semiconductor substrate in a direction of extension of the second electrode and a length by which the third electrode protrudes from the second semiconductor layer to the semiconductor substrate in a direction of extension of the third electrode are equal to each other.
11 . The semiconductor device according to claim 1 , wherein
a size of the first electrode in a direction orthogonal to a direction of extension of the first electrode is smaller than each of a size of the second electrode in a direction orthogonal to a direction of extension of the second electrode and a size of the third electrode in a direction orthogonal to a direction of extension of the third electrode.
12 . The semiconductor device according to claim 1 , wherein
spacing between the second electrode and the third electrode adjacent to each other, spacing between the second electrodes adjacent to each other, or spacing between the third electrodes adjacent to each other along a direction in which the second electrode and the third electrode are arranged is 15 μm or less.
13 . The semiconductor device according to claim 1 , wherein
the third electrode is located on each of one side and the other side of the first electrode in a direction in which the first electrode and the third electrode are arranged, and
spacing between the third electrode located on the one side of the first electrode and the third electrode located on the other side of the first electrode is 15 μm or less in the direction.
14 . A semiconductor device control method of controlling the semiconductor device according to claim 1 , wherein
a first signal is provided to the first electrode,
a second signal is provided to the second electrode, and
when the semiconductor device is turned off by transition of each of the first signal and the second signal, the first signal transitions later than the second signal.
15 . The semiconductor device control method according to claim 14 , wherein
the first conductivity type is an N type, and the second signal transitions at a potential equal to or less than zero with respect to the third electrode.
16 . A semiconductor device manufacturing method of manufacturing the semiconductor device according to claim 5 , wherein
prior to formation of the first semiconductor layer and the second semiconductor layer, impurities of the first conductivity type are introduced into a first region of the semiconductor substrate in a first introduction amount and into a second region of the semiconductor substrate in a second introduction amount greater than the first introduction amount, and
the impurities of the first conductivity type introduced into the first region and the impurities of the first conductivity type introduced into the second region are diffused in parallel to form the first semiconductor layer and the second semiconductor layer.
17 . The semiconductor device manufacturing method according to claim 16 , wherein
the impurities of the first conductivity type are introduced into the first region in the first introduction amount and into the second region in the second introduction amount in parallel by ion implantation using a mask having a stripe pattern or a dot pattern.
18 . A semiconductor device manufacturing method of manufacturing the semiconductor device according to claim 10 , wherein
prior to formation of the second electrode and the third electrode, a trench in which the second electrode is embedded and a trench in which the third electrode is embedded are formed in parallel by selective etching using an opening mask.
19 . A semiconductor device manufacturing method of manufacturing the semiconductor device according to claim 11 , wherein
prior to formation of the first electrode, the second electrode, and the third electrode, a first trench in which the first electrode is embedded, a second trench in which the second electrode is embedded, and a third trench in which the third electrode is embedded are formed in parallel by selective etching using an opening mask, and an opening used for etching to form the second trench and an opening used for etching to form the third trench are each wider than an opening used for etching to form the first trench.