Semiconductor device having an injection suppression region
Provided is a semiconductor device which includes a semiconductor substrate including a transistor portion and a diode portion. The transistor portion includes an injection suppression region that suppresses injection of a carrier of a second conductivity type at an end portion on the diode portion side in a top view of the semiconductor substrate. Both the transistor portion and the diode portion include a base region of a second conductivity type on a front surface of the semiconductor substrate, the transistor portion further includes an emitter region of a first conductivity type and an extraction region of a second conductivity type having a higher doping concentration than the base region on the front surface of the semiconductor substrate, and the injection suppression region is not provided with the emitter region and the extraction region.
1 . A semiconductor device comprising:
a semiconductor substrate including a well region, a transistor portion, and a diode portion,
wherein the transistor portion includes an injection suppression region configured to suppress injection of a carrier of a second conductivity type at an end portion on the diode portion side in a top view of the semiconductor substrate, and the injection suppression region extends along a boundary between the transistor portion and the diode portion;
a plurality of trench portions configured to extend in an extending direction of the transistor portion and the diode portion to be arranged in an arrangement direction,
wherein both the transistor portion and the diode portion have a base region of a second conductivity type in a front surface of the semiconductor substrate,
wherein the transistor portion further includes an emitter region of a first conductivity type and an extraction region of a second conductivity type having a higher doping concentration than the base region in the front surface of the semiconductor substrate,
wherein the plurality of trench portions include gate trench portions and dummy trench portions,
wherein each of the gate trench portions includes gate trench straight portions such that the plurality of trench portions include gate trench straight portions,
wherein each of the dummy trench portions includes at least one dummy trench straight portion such that the plurality of trench portions include dummy trench straight portions, and
wherein a region including the injection suppression region and extending up to the well region in the extending direction in plan view is not provided with the emitter region and the extraction region from each dummy trench straight portion, located at least in part in the injection suppression region, to another nearest dummy trench straight portion, located at least in part in the injection suppression region, in the arrangement direction of the plurality of trench portions.
2 . The semiconductor device according to claim 1 ,
wherein a width of the injection suppression region in an arrangement direction of the transistor portion and the diode portion ranges from 20 μm to 900 μm in a top view of the semiconductor substrate.
3 . The semiconductor device according to claim 1 ,
wherein the injection suppression region is further provided between an end portion of the diode portion in the extending direction and an outer periphery of an active region in a top view of the semiconductor substrate.
4 . The semiconductor device according to claim 1 ,
wherein an area of the diode portion is 10% or more of a total area of the diode portion and the injection suppression region in a top view of the semiconductor substrate.
5 . The semiconductor device according to claim 1 ,
wherein a total area of the diode portion ranges from 1.4% to 22% of an area of the semiconductor device in a top view of the semiconductor substrate.
6 . The semiconductor device according to claim 1 ,
wherein a doping concentration of the base region in the injection suppression region is equal to or less than a doping concentration of the base region of the diode portion.
7 . The semiconductor device according to claim 6 ,
wherein a doping concentration of the base region in the injection suppression region ranges from 1E+16 cm −3 to 5E+19 cm −3 .
8 . The semiconductor device according to claim 1 ,
wherein a doping concentration of the base region of the diode portion ranges from 1E+16 cm −3 to 1E+18 cm −3 .
9 . The semiconductor device according to claim 1 ,
wherein a doping concentration of the extraction region ranges from 5E+18 cm −3 to 5E+20 cm −3 .
10 . The semiconductor device according to claim 1 ,
wherein the plurality of trench portions include a gate trench portion and a dummy trench portion, and
wherein the injection suppression region includes a dummy trench portion and does not include a gate trench portion.
11 . The semiconductor device according to claim 1 ,
wherein a dummy ratio is defined as a ratio of the number of dummy trench straight portions to a total number of gate trench straight portions and dummy trench straight portions encountered in cross sectional view in the arrangement direction in a specified portion or region of the semiconductor substrate that is specified when referring to any particular dummy ratio, and
wherein the dummy ratio in the injection suppression region is higher than the dummy ratio in the transistor portion excluding the injection suppression region in a cross sectional view in the arrangement direction through the transistor portion and the injection suppression region.
12 . The semiconductor device according to claim 11 ,
wherein the dummy ratio in the transistor portion excluding the injection suppression region, in a cross sectional view in the arrangement direction through the transistor portion and the injection suppression region, ranges from 0% to 75%.
13 . The semiconductor device according to claim 1 , further comprising:
an accumulation region of a first conductivity type inside the semiconductor substrate.
14 . The semiconductor device according to claim 1 , further comprising:
a mesa defined by a dummy trench portion is provided in the transistor portion adjacent the injection suppression region, wherein the mesa defined by the dummy trench portion in the transistor portion adjacent the injection suppression region is provided with the extraction region.
15 . The semiconductor device according to claim 1 , wherein the transistor portion includes a collector region and wherein the injection suppression region is provided over the collector region in a top view of the semiconductor substrate.