IP Library › Granted Patent US 12,470,228
Granted Patent B2
US 12,470,228 · App. 18/414,501 · Granted Nov 11, 2025

Signal receiving circuit and calibration method thereof

Inventor: Yi-Chang Shih (Hsinchu, TW)
Assignee: REALTEK SEMICONDUCTOR CORPORATION
H03M1/1019H03M1/1023
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Quick Facts
Patent No.
US 12,470,228
App. No.
18/414,501
Granted
Nov 11, 2025
Kind
B2
Abstract

A signal receiving circuit receives an input signal and includes a radio frequency (RF) front-end circuit, a filter circuit, an amplifier circuit, an analog-to-digital converter (ADC), a compensation circuit, an adder circuit, and a control circuit. The RF front-end circuit down-converts the input signal to generate a down-converted signal. The filter circuit filters the down-converted signal to generate a filtered signal. The amplifier circuit amplifies, according to a control signal, the filtered signal with a gain to generate an amplified signal. The ADC converts the amplified signal into a first digital code. The compensation circuit generates a compensation code according to at least one of the control signal and the gain. The adder circuit generates a second digital code according to the compensation code and the first digital code. The control circuit generates the control signal according to the second digital code.

Claims (25)

1 . A signal receiving circuit configured to receive an input signal, the signal receiving circuit comprising:

a radio frequency (RF) front-end circuit configured to down-convert the input signal to generate a down-converted signal;

a filter circuit coupled to the RF front-end circuit and configured to filter the down-converted signal to generate a filtered signal;

an amplifier circuit coupled to the filter circuit and configured to amplify, according to a control signal, the filtered signal with a gain to generate an amplified signal;

an analog-to-digital converter (ADC) coupled to the amplifier circuit and configured to convert the amplified signal into a first digital code;

a compensation circuit coupled to the amplifier circuit and configured to generate a compensation code according to at least one of the control signal and the gain;

an adder circuit coupled to the compensation circuit and the ADC and configured to generate a second digital code according to the compensation code and the first digital code; and

a control circuit coupled to the amplifier circuit and the adder circuit and configured to generate the control signal according to the second digital code.

2 . The signal receiving circuit of claim 1 , wherein the compensation code is used to compensate a direct current (DC) offset of the ADC.

3 . The signal receiving circuit of claim 1 further comprising:

a high-pass filter (HPF) coupled to the filter circuit and configured to filter the filtered signal to filter out at least one of a direct current (DC) offset of the RF front-end circuit and a DC offset of the filter circuit.

4 . The signal receiving circuit of claim 3 , wherein the HPF comprises:

a capacitor having a first end and a second end, wherein the first end is coupled to the filter circuit, and the second end is coupled to the amplifier circuit; and

a resistor having a third end and a fourth end, wherein the third end is coupled to the amplifier circuit, and the fourth end is coupled to a reference voltage.

5 . The signal receiving circuit of claim 1 , wherein the compensation circuit further determines a look-up table according to a piece of temperature information, and the compensation circuit uses at least one of the control signal and the gain as an index to obtain the compensation code from the look-up table.

6 . A method of calibrating a signal receiving circuit, wherein the signal receiving circuit comprises an amplifier circuit and an analog-to-digital converter (ADC), the ADC is configured to convert an output signal of the amplifier circuit to generate a first digital code, the method comprising:

generating a control signal according to a second digital code, the control signal being used to control a gain of the amplifier circuit;

generating a compensation code according to at least one of the control signal and the gain; and

generating the second digital code according to the compensation code and the first digital code.

7 . The method of claim 6 , wherein the compensation code is used to compensate a direct current (DC) offset of the ADC.

8 . The method of claim 6 , wherein the signal receiving circuit further comprises a radio frequency (RF) front-end circuit and a filter circuit, the filter circuit generates a filtered signal, the method further comprising:

filtering out at least one of a direct current (DC) offset of the RF front-end circuit and a DC offset of the filter circuit by high-pass filtering the filtered signal before the amplifier circuit amplifies the filtered signal.

9 . The method of claim 6 further comprising:

determining a look-up table according to a piece of temperature information;

wherein at least one of the control signal and the gain is an index of the look-up table, and the compensation code corresponds to the index.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 17, 2024
From: SHIH, YI-CHANG
To: REALTEK SEMICONDUCTOR CORPORATION
Reel/Frame 066141/0511 →
Priority Claims (1)
TW 112104244 · Feb 7, 2023 · national
Continuity (1)
Related Publication 20240267054A1 · Aug 8, 2024
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