Pixel driving circuit and display device
The present embodiments disclose a pixel. A pixel according to an embodiment of the present disclosure comprises a luminous element and a pixel circuit connected to the luminous element, wherein the pixel circuit include a first pixel circuit configured to control light-emission and non-emission of the luminous element in response to a control signal applied to each of a plurality of subframes constituting a single frame during a light-emitting period, a second pixel circuit configured to store bit values of image data in a data writing period and generate the control signal based on the bit values and a clock signal, a bias circuit configured to supply a driving power to the first pixel circuit, and a bias controller configured to generate a bias control signal for controlling the bias circuit and output the bias control signal to the bias circuit.
1. A pixel comprising a luminous element and a pixel circuit connected to the luminous element,
wherein the pixel circuit includes:
a first pixel circuit configured to control light-emission and non-emission of the luminous element in response to a control signal applied to each of a plurality of subframes constituting a single frame during a light-emitting period;
a second pixel circuit configured to store bit values of image data in a data writing period and generate the control signal based on the bit values and a clock signal;
a bias circuit configured to supply a driving power to the first pixel circuit; and
a bias controller configured to generate a bias control signal for controlling the bias circuit and output the bias control signal to the bias circuit,
wherein the second pixel circuit is further configured to store bit values of bias control data, and the bias controller is configured to generate the bias control signal based on the bias control data,
wherein the bias control data defines a number of operations of the bias circuit in the single frame.
2. A pixel comprising a luminous element and a pixel circuit connected to the luminous element,
wherein the pixel circuit includes:
a first pixel circuit configured to control light-emission and non-emission of the luminous element in response to a control signal applied to each of a plurality of subframes constituting a single frame during a light-emitting period;
a second pixel circuit configured to store bit values of image data in a data writing period and generate the control signal based on the bit values of image data and a clock signal;
a bias circuit configured to supply a driving power to the first pixel circuit; and
a bias controller configured to generate a bias control signal for controlling the bias circuit and output the bias control signal to the bias circuit,
wherein the first pixel circuit includes a driver,
the driver includes a capacitor charged by the driving power, and
the bias controller configured to control the bias circuit such that the bias circuit stops supplying the driving power when the capacitor is charged with the driving power.
3. A pixel comprising a luminous element and a pixel circuit connected to the luminous element,
wherein the pixel circuit includes:
a first pixel circuit configured to control light-emission and non-emission of the luminous element in response to a control signal applied to each of a plurality of subframes constituting a single frame during a light-emitting period;
a second pixel circuit configured to store bit values of image data in a data writing period and generate the control signal based on the bit values and a clock signal;
a bias circuit configured to supply a driving power to the first pixel circuit; and
a bias controller configured to generate a bias control signal for controlling the bias circuit and output the bias control signal to the bias circuit,
wherein the first pixel circuit includes:
a first transistor configured to output a driving current; and
a second transistor configured to transmit or block the driving current to the luminous element according to the control signal,
wherein the second pixel circuit includes:
a memory configured to store the bit values of the image data; and
a pulse width modulation (PWM) controller configured to read the bit values of the image data from the memory and determine a pulse width of the control signal for a subframe based on a length of the subframe and a bit value corresponding to the subframe.