Granted Patent B2

US 12,413,241 · App. 18/427,585 · Granted Sep 9, 2025

Inventor: Naveen Raj (Chandler, AZ)

Assignee: Microchip Technology Incorporated

H03M1/662

Abstract

Claims (79)

1. A system, comprising:

a digital-to-analog converter (DAC) system to process a digital input signal including a series of digital input codes, the DAC system comprising:

a first DAC circuitry; and

a second DAC circuitry;

an input splitter circuitry connected to the DAC system to:

receive a first digital input code of the series of digital input codes, the first digital input code having a first value;

based on the first value of the received first digital input code, transfer the first digital input code to the first DAC circuitry;

receive a second digital input code of the series of digital input codes, the second digital input code having a second value different than the first value; and

based on the second value of the received second digital input code:

divide the second digital input code into (a) a second digital input code primary component and (b) a second digital input code secondary component;

transfer the second digital input code primary component to the first DAC circuitry; and

transfer the second digital input code secondary component to the second DAC circuitry;

the first DAC circuitry comprising circuitry to:

convert the first digital input code to a first analog output signal;

convert the second digital input code primary component to a second analog output signal primary component; and

the second DAC circuitry comprising circuitry to:

convert the second digital input code secondary component to a second analog output signal secondary component; and

an adding circuitry, connected with the first DAC circuitry and the second DAC circuitry, to combine the second analog output signal primary component and the second analog output signal secondary component to provide a combined second analog output signal.

2. The system of claim 1 , wherein the adding circuitry comprises an operational amplifier.

3. The system of claim 1 , wherein the adding circuitry comprises a Schottky diode.

4. The system of claim 3 , wherein the value of the second digital input code secondary component is determined based at least on a voltage drop across the Schottky diode.

5. The system of claim 1 , wherein the input splitter circuitry to:

receive a third digital input code of the series of digital input codes, the third digital input code having a third value greater than the second value of the second digital input code; and

based on the third value of the third digital input code:

divide the third digital input code into:

(a) a third digital input code primary component having the same value as the second digital input code primary component of the second digital input code, and

(b) a third digital input code secondary component having a greater value than the second digital input code secondary component of the second digital input code.

6. The system of claim 1 , wherein:

the input splitter circuitry stores or has access to at least one high-error input code range; and

the input splitter circuitry to:

determine the first value of the received first digital input code is not included in the at least one high-error input code range, and in response, to transfer the received first digital input code to the first DAC circuitry; and

determine the second value of the received second digital input code is included in a respective high-error input code range of the at least one high-error input code range, and in response, to divide the second digital input code into (a) the second digital input code primary component and (b) the second digital input code secondary component.

7. The system of claim 6 , wherein:

the second digital input code primary component of the second digital input code is defined with a value preceding the respective high-error input code range; and

the second digital input code secondary component is determined based on a difference between the second digital input code and the second digital input code primary component.

8. The system of claim 1 , wherein a same reference voltage is applied to both the first DAC circuitry and the second DAC circuitry.

9. The system of claim 1 , wherein a first reference voltage is applied to the first DAC circuitry, and a second reference voltage different from the first reference voltage is applied to second DAC circuitry.

10. A method, comprising:

receiving a digital input signal including a series of digital input codes including (a) a first digital input code not included in a high-error input code range and (b) a second digital input code included in the high-error input code range;

determining, by an input splitter circuitry, that the first digital input code is not included in the high-error input code range, and in response, converting the first digital input code, by a first DAC circuitry, to a first analog output signal;

determining, by the input splitter circuitry, that the second digital input code is included in the high-error input code range, and in response:

dividing the second digital input code into a second digital input code primary component and a second digital input code secondary component;

converting, by the first DAC circuitry, the second digital input code primary component to a second analog output signal primary component;

converting, by a second DAC circuitry, the second digital input code secondary component to a second analog output signal secondary component; and

combining, by an adding circuitry connected with the first DAC circuitry and the second DAC circuitry, the second analog output signal primary component and the second analog output signal secondary component to provide a combined second analog output signal.

11. The method of claim 10 , wherein the adding circuitry comprises an operational amplifier.

12. The method of claim 10 , wherein:

the adding circuitry comprises a Schottky diode; and

the second digital input code secondary component is determined based at least on a voltage drop across the Schottky diode.

13. The method of claim 12 , comprising:

receiving a third digital input code of the series of digital input codes, the third digital input code having a greater value than the second digital input code; and

determining, by the input splitter circuitry, the third digital input code is included in the high-error input code range, and in response:

dividing the third digital input code into:

(a) a third digital input code primary component having the same value as the second digital input code primary component of the second digital input code, and

(b) a third digital input code secondary component having a greater value than the second digital input code secondary component of the second digital input code;

converting, by the first DAC circuitry, the third digital input code primary component to a third analog output signal primary component;

converting, by the second DAC circuitry, the third digital input code secondary component to a third analog output signal secondary component; and

combining, by the adding circuitry, the third analog output signal primary component and the third analog output signal secondary component to provide a combined third analog output signal.

14. The method of claim 10 , wherein:

the second digital input code primary component of the second digital input code is defined by a highest value of a low-error input code range preceding the high-error input code range; and

the second digital input code secondary component is determined based on a difference between the second digital input code and the second digital input code primary component.

15. The method of claim 14 , wherein:

the adding circuitry comprises a Schottky diode; and

the second digital input code secondary component is determined based on (a) the difference between the second digital input code and the second digital input code primary component and (b) a voltage drop across the Schottky diode.

16. A system, comprising:

non-transitory memory storing at least one high-error input code range; and

circuitry to:

receive a series of digital input codes;

determine whether respective digital input codes are included in the stored at least one high-error input code range;

for a first digital input code determined not to be in the at least one high-error input code range, use a first digital-to-analog converter (DAC) circuitry to convert the respective digital input code to a first analog output signal; and

for a second digital input code determined to be in the at least one high-error input code range:

divide the second digital input code into (a) a second digital input code primary component and (b) a second digital input code secondary component;

use the first DAC circuitry to convert the second digital input code primary component to a second analog output signal primary component;

use the second DAC circuitry to convert the second digital input code secondary component to a second analog output signal secondary component; and

use an adding circuitry to combine the second analog output signal primary component and the second analog output signal secondary component to provide a combined second analog output signal.

17. The system of claim 16 , wherein the non-transitory memory stores multiple high-error input code ranges separated by respective non-high-error input code ranges.

18. The system of claim 16 , wherein the adding circuitry comprises an operational amplifier.

19. The system of claim 16 , wherein the adding circuitry comprises a Schottky diode.

20. The system of claim 19 , wherein the second digital input code secondary component is determined based at least on a voltage drop across the Schottky diode.

Assignments (1)

Continuity (2)

References Cited (17)