IP Library › Granted Patent US 12,451,901
Granted Patent B2
US 12,451,901 · App. 18/231,371 · Granted Oct 21, 2025

Circuitry for converting a digital signal to an analog signal

Inventor: Naveen Raj (Chandler, AZ)
Assignee: Microchip Technology Incorporated
H03M1/74
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Quick Facts
Patent No.
US 12,451,901
App. No.
18/231,371
Granted
Oct 21, 2025
Kind
B2
Abstract

The disclosure relates to circuitry, systems, and methods for digital-to-analog conversion. In various examples, a corresponding circuitry may comprise a first digital-to-analog conversion circuit to provide a first analog output signal and a second digital-to-analog conversion circuit to provide a second analog output signal. The circuitry may comprise addition circuitry to provide a combined analog output signal from the first analog output signal and the second analog output signal. A first voltage reference circuit, connected with the first digital-to-analog conversion circuit to provide a first reference voltage and a second voltage reference circuit, connected with the second digital-to-analog conversion circuit to provide a second reference voltage may be provided. The first reference voltage and the second reference voltage may differ from each other.

Claims (48)

1. A circuitry, comprising:

a first digital-to-analog conversion circuit, comprising a first digital input and a first analog output, the first analog output to provide a first analog output signal;

a second digital-to-analog conversion circuit, comprising a second digital input and a second analog output, the second analog output to provide a second analog output signal;

an addition circuitry, connected with the first analog output and the second analog output, the addition circuitry to provide a combined analog output signal from the first analog output signal and the second analog output signal;

a first voltage reference circuit, connected with the first digital-to-analog conversion circuit to provide a first reference voltage; and

a second voltage reference circuit, connected with the second digital-to-analog conversion circuit to provide a second reference voltage; and

a control circuit with at least:

a digital input;

a first digital output, connected with the first digital input of the first digital-to-analog conversion circuit, and

a second digital output, connected with the second digital input of the second digital-to-analog conversion circuit:

wherein

the first reference voltage and the second reference voltage differ from each other and wherein

the control circuit to provide at least a first digital output signal provided at the first digital output and a second digital output signal provided at the second digital output, from a digital input signal, received at the digital input.

2. The circuitry of claim 1 , wherein the digital input signal represents one or more samples with a number of bits per sample and the control circuit to provide the first digital output signal with one or more samples having a predefined number of most significant bits of the respective samples of the digital input signal, and the control circuit to provide the second digital output signal with one or more samples having a predefined number of least significant bits of the respective samples of the digital input signal.

3. The circuitry of claim 2 , wherein the number of most significant bits plus the number of least significant bits correspond to the number of bits per sample of the digital input signal.

4. The circuitry of claim 2 , wherein the predefined number of most significant bits corresponds to a resolution of the first digital-to-analog conversion circuit.

5. The circuitry of claim 3 , wherein the predefined number of most significant bits corresponds to a resolution of the first digital-to-analog conversion circuit.

6. The circuitry of claim 1 , wherein the second reference voltage is less than the first reference voltage.

7. The circuitry of claim 1 , wherein the second reference voltage is set to correspond to the first reference voltage divided by two to the power of the number of bits applied to the second digital-to-analog conversion circuit.

8. The circuitry of claim 1 , wherein a resolution of the first digital-to-analog conversion circuit corresponds to a resolution of the second digital-to-analog conversion circuit.

9. The circuitry of claim 1 , wherein the first digital-to-analog conversion circuit and the second digital-to-analog conversion circuit have a resolution of at least 12 bits.

10. The circuitry of claim 1 , wherein the first digital-to-analog conversion circuit and the second digital-to-analog conversion circuit are formed integrally.

11. The circuitry of claim 1 , wherein the first digital-to-analog conversion circuit and the second digital-to-analog conversion circuit are formed by a multi-channel digital-to-analog converter.

12. The circuitry of claim 1 , wherein one or more of the first voltage reference circuit and the second voltage reference circuit comprise at least one high precision buffered voltage reference.

13. The circuitry of claim 1 , wherein the digital input signal has a bit depth that is greater than a resolution of one or more of the first digital-to-analog conversion circuit and the second digital-to-analog conversion circuit.

14. The circuitry of claim 1 , wherein the addition circuitry comprises one or more of an operational amplifier and a Schottky diode.

15. A system, comprising:

a first voltage reference circuit to provide a first reference voltage;

a second voltage reference circuit to provide a second reference voltage, wherein the first reference voltage and the second reference voltage differ from each other;

first circuitry; and

second circuitry; wherein

the first circuitry comprises:

a first digital-to-analog conversion circuit, comprising a first digital input and a first analog output, the first digital-to-analog conversion circuit being connected to the first voltage reference circuit to receive the first reference voltage;

a second digital-to-analog conversion circuit, comprising a second digital input and a second analog output, the second digital-to-analog conversion circuit being connected to the second voltage reference circuit to receive the second reference voltage; and

first addition circuitry, connected with the first analog output and the second analog output and to provide a first combined analog output from the first analog output and the second analog output; and wherein

the second circuitry comprises:

a third digital-to-analog conversion circuit, comprising a third digital input and a third analog output, the third digital-to-analog conversion circuit being connected to the first voltage reference circuit to receive the first reference voltage;

a fourth digital-to-analog conversion circuit, comprising a fourth digital input and a fourth analog output, the fourth digital-to-analog conversion circuit being connected to the second voltage reference circuit to receive the second reference voltage; and

second addition circuitry, connected with the third analog output and the fourth analog output, the second addition circuitry to provide a combined second analog output from the third analog output and the fourth analog output.

16. A method, comprising:

providing a first digital-to-analog conversion circuit with a first reference voltage;

providing a second digital-to-analog conversion circuit with a second reference voltage, wherein the first reference voltage and the second reference voltage differ from each other;

providing a predefined number of most significant bits of a digital input signal to the first digital-to-analog conversion circuit;

providing a predefined number of least significant bits of the digital input signal to the second digital-to-analog conversion circuit; and

combining an analog output of the first digital-to-analog conversion circuit with an analog output of the second digital-to-analog conversion circuit to obtain a combined analog output signal, wherein

the predefined number of most significant bits and the predefined number of least significant bits are provided so that the predefined number of most significant bits plus the predefined number of least significant I its correspond to a number of bits of the digital input signal.

17. The method of claim 16 , comprising controlling the second reference voltage to be less than the first reference voltage.

18. The method of claim 16 , comprising controlling the second reference voltage to correspond to the first reference voltage divided by two to the power of the number of least significant bits.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 8, 2023
From: RAJ, NAVEEN
To: MICROCHIP TECHNOLOGY INCORPORATED
Reel/Frame 064520/0480 →
Continuity (2)
Provisional Application 63447125 · Feb 21, 2023
Related Publication 20240283461A1 · Aug 22, 2024
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