Pulse width modulation signal generation circuit and lamp control system including the same
Disclosed are a pulse width modulation (PWM) signal generation circuit and a lamp control system including the same. The PWM signal generation circuit includes a counting circuit configured to generate a counting signal, a pulse period control circuit configured to convert the counting signal into a first analog output signal and compare the first analog output signal with a first comparison voltage to generate a first output signal, a pulse width control circuit configured to convert the counting signal into a second analog output signal and to compare the second analog output signal with a second comparison voltage to generate a second output signal, and a control logic circuit configured to determine a period of a PWM signal based on the first output signal, determine a pulse width of the PWM signal based on the second output signal, and output the PWM signal having the period and the pulse width.
1 . A pulse width modulation (PWM) signal generation circuit comprising:
a counting circuit configured to generate a counting signal by counting one of a rising edge and a falling edge of a clock signal;
a pulse period control circuit configured to convert the counting signal into a first analog output signal and to compare the first analog output signal with a first comparison voltage to generate a first output signal corresponding to a result of comparison;
a pulse width control circuit configured to convert the counting signal into a second analog output signal and to compare the second analog output signal with a second comparison voltage to generate a second output signal corresponding to a result of comparison; and
a control logic circuit configured to:
determine a period of a PWM signal based on the first output signal;
determine a pulse width of the PWM signal based on the second output signal; and
output the PWM signal having the period and the pulse width,
wherein the pulse period control circuit comprises:
a first digital-to-analog conversion circuit configured to output, as the first analog output signal, a voltage corresponding to the counting signal among voltages less than or equal to a first reference voltage and greater than or equal to a second reference voltage; and
a first comparison circuit configured to:
receive the first comparison voltage via a non-inverting input terminal and receive the first analog output signal via an inverting input terminal;
compare the first comparison voltage with the first analog output signal;
output the first output signal in a first state based on the first analog output signal being less than the first comparison voltage; and
output the first output signal transitioned from the first state to a second state via an output terminal based on the first analog output signal being greater than the first comparison voltage, and
wherein the pulse width control circuit comprises:
a second digital-to-analog conversion circuit configured to output, as the second analog output signal, a voltage corresponding to the counting signal among voltages less than or equal to a third reference voltage and greater than or equal to a fourth reference voltage; and
a second comparison circuit configured to:
receive the second comparison voltage via a non-inverting input terminal and receive the second analog output signal via an inverting input terminal;
compare the second comparison voltage with the second analog output signal;
output the second output signal in a first state based on the second analog output signal being less than the second comparison voltage; and
output the second output signal transitioned from the first state to a second state via an output terminal based on the second analog output signal being greater than the second comparison voltage.
2 . The PWM signal generation circuit of claim 1 , wherein the control logic circuit determines the period of the PWM signal according to Equation 1 below:
T
1
=
VREF
1
/
[
VREFP
1
-
VREFP
2
2
N
1
]
×
1
/
CLK
,
Equation
l
wherein:
VREF 1 denotes the first comparison voltage;
VREFP 1 denotes the first reference voltage;
VREFP 2 denotes the second reference voltage;
N 1 denotes the number of bits of the first analog output signal; and
CLK denotes a period of the clock signal.
3 . The PWM signal generation circuit of claim 1 , wherein the control logic circuit determines the period of the PWM signal according to Equation 2 below:
T
2
=
VREF
2
/
[
VREFP
3
-
VREFP
4
2
N
2
]
×
1
/
CLK
,
Equation
2
wherein:
VREF 2 denotes the second comparison voltage;
VREFP 3 denotes the third reference voltage;
VREFP 4 denotes the fourth reference voltage;
N 2 denotes the number of bits of the second analog output signal; and
CLK denotes a period of the clock signal.
4 . The PWM signal generation circuit of claim 1 , wherein the control logic circuit is configured to determine a reset timing of the counting signal based on a change in level of the first output signal to provide a reset signal to the counting circuit.
5 . The PWM signal generation circuit of claim 1 , wherein the control logic circuit is configured to generate a reset signal and provide the reset signal to the counting circuit, the reset signal transitioning from a high level to a low level at a moment when the first output signal transitions from the first state to the second state.