Display panel including test pixel
A display panel includes a substrate including a display area, and a peripheral area surrounding the display area in plan view, a pixel circuit in the display area, a light-emitting diode in the display area, electrically connected to the pixel circuit, and including a pixel electrode, an opposite electrode, and an emission layer between the pixel electrode and the opposite electrode, a test circuit in the peripheral area, and a pseudo-diode in the peripheral area, electrically connected to the test circuit, and including a first transistor.
1. A display panel comprising:
a substrate comprising a display area, and a peripheral area surrounding the display area in plan view;
a pixel circuit in the display area;
a light-emitting diode in the display area, electrically connected to the pixel circuit, and comprising a pixel electrode, an opposite electrode, and an emission layer between the pixel electrode and the opposite electrode;
a test circuit in the peripheral area; and
a pseudo-diode in the peripheral area, electrically connected to the test circuit, comprising a first transistor, and configured such that one or more electrical characteristics of the pseudo-diode are able to be adjusted to more closely match one or more electrical characteristics of the light-emitting diode.
2. The display panel of claim 1 , wherein the first transistor comprises a semiconductor layer, a gate electrode above the semiconductor layer, and a control electrode below the semiconductor layer.
3. The display panel of claim 2 , wherein the semiconductor layer comprises an active region overlapping the gate electrode, and a drain region and a source region on respective sides of the active region, and
wherein the gate electrode is electrically connected to the drain region.
4. The display panel of claim 1 , wherein the pseudo-diode further comprises a second transistor connected to the first transistor in series.
5. The display panel of claim 1 , further comprising:
pads in the peripheral area; and
connection lines electrically connecting the pads to the test circuit and to the pseudo-diode.
6. The display panel of claim 5 , wherein the test circuit and the pseudo-diode are adjacent to the pads.
7. The display panel of claim 5 , wherein the connection lines comprise a first connection line electrically connecting a first pad of the pads to a control electrode of the first transistor, and
wherein the first pad and the first connection line are configured to transfer a control voltage from a power supply to the control electrode.
8. The display panel of claim 7 , wherein the control voltage is configured to be adjusted such that a V-I curve of the pseudo-diode and a V-I curve of the light-emitting diode have similar shapes to each other.
9. The display panel of claim 5 , wherein the connection lines comprise a second connection line electrically connecting a second pad of the pads to the test circuit and to the pseudo-diode, and
wherein the second pad and the second connection line are configured to transfer a test current from the pseudo-diode to a measurement circuit.
10. The display panel of claim 9 , wherein the connection lines further comprise a third connection line electrically connected to a third pad of the pads that is grounded, and a fourth connection line electrically connected to a fourth pad of the pads that is grounded, and
wherein each of the third connection line and the fourth connection line surrounds at least a portion of the second connection line in the plan view.
11. A display panel comprising a pixel in a display area, and a test pixel in a peripheral area,
wherein the pixel comprises a pixel circuit, and a light-emitting diode electrically connected to the pixel circuit, and
wherein the test pixel comprises:
a test circuit comprising:
a driving transistor comprising a driving gate electrically connected to a first node, a first terminal, and a second terminal electrically connected to a second node;
a data writing transistor electrically connected between the first node and a data line;
a compensation transistor electrically connected between the first node and a first voltage line;
an initialization transistor electrically connected between the second node and a second voltage line;
an emission control transistor electrically connected between the first terminal of the driving transistor and a third voltage line;
a storage capacitor electrically connected between the first node and the second node; and
a holding capacitor electrically connected between the third voltage line and the second node; and
a pseudo-diode electrically connected to the test circuit, not configured to emit light, electrically connected between the second node and a fourth voltage line, and configured such that one or more electrical characteristics of the pseudo-diode are able to be adjusted to more closely match one or more electrical characteristics of the light-emitting diode.
12. The display panel of claim 11 , wherein the pseudo-diode comprises a gate, a first terminal electrically connected to the gate of the pseudo-diode and to the second node, a second terminal electrically connected to the fourth voltage line, and a control electrode electrically connected to a fifth voltage line.
13. The display panel of claim 11 , wherein the test pixel operates in a first period and a second period during one frame period, and
wherein the first period comprises:
a first initialization period during which the compensation transistor and the initialization transistor are turned on, a first voltage is received from the first voltage line through the compensation transistor that is turned on, and a second voltage is received from the second voltage line through the initialization transistor that is turned on; and
a second initialization period during which the initialization transistor is turned on, and the second voltage is received from the second voltage line through the initialization transistor that is turned on.
14. The display panel of claim 13 , wherein, during the second period, the emission control transistor is turned on, and a third voltage is supplied to the first terminal of the driving transistor through the emission control transistor that is turned on.
15. The display panel of claim 13 , wherein the test pixel is connected to a measurement circuit through a connection line electrically connecting the test pixel to a pad, and
wherein the measurement circuit is configured to measure a test current flowing through the pseudo-diode during the second period.
16. The display panel of claim 11 , wherein the pixel circuit comprises:
a driving transistor comprising a driving gate electrically connected to a first node, a first terminal, and a second terminal electrically connected to a second node;
a data writing transistor electrically connected between the first node of the pixel circuit and a data line;
a compensation transistor electrically connected between the first node of the pixel circuit and a first voltage line;
an initialization transistor electrically connected between the second node of the pixel circuit and a second voltage line;
an emission control transistor electrically connected between the first terminal of the driving transistor of the pixel circuit and a third voltage line;
a storage capacitor electrically connected between the first node of the pixel circuit and the second node of the pixel circuit; and
a holding capacitor electrically connected between the third voltage line and the second node of the pixel circuit,
wherein the light-emitting diode is electrically connected to the second node of the pixel circuit.
17. The display panel of claim 16 , wherein the pixel is configured to operate in a first period and a second period during one frame period, and
wherein, during the second period, the emission control transistor of the pixel circuit is turned on, and a third voltage is supplied to the first terminal of the driving transistor of the pixel circuit through the emission control transistor that is turned on to allow the light-emitting diode to emit light.
18. The display panel of claim 16 , wherein the light-emitting diode comprises a pixel electrode, an opposite electrode, and an emission layer between the pixel electrode and the opposite electrode, and
wherein a voltage applied to the opposite electrode of the light-emitting diode and a fourth voltage applied to the fourth voltage line have substantially a same magnitude.
19. The display panel of claim 11 , wherein the pixel is provided in plurality comprising a first pixel for emitting light in a first color, and a second pixel for emitting light in a second color that is different from the first color, and
wherein the test pixel is provided in plurality comprising a first test pixel corresponding to the first pixel, and a second test pixel corresponding to the second pixel.
20. A display panel comprising a pixel in a display area, and a test pixel in a peripheral area,
wherein the pixel comprises a pixel circuit, and a light-emitting diode electrically connected to the pixel circuit, and
wherein the test pixel comprises:
a test circuit comprising:
a driving transistor comprising a driving gate electrically connected to a first node, a first terminal, and a second terminal electrically connected to a second node;
a data writing transistor electrically connected between the first node and a data line;
a compensation transistor electrically connected between the first node and a first voltage line;
an initialization transistor electrically connected between the second node and a second voltage line;
an emission control transistor electrically connected between the first terminal of the driving transistor and a third voltage line;
a storage capacitor electrically connected between the first node and the second node; and
a holding capacitor electrically connected between the third voltage line and the second node; and
a pseudo-diode electrically connected to the test circuit, not configured to emit light, and electrically connected between the second node and a fourth voltage line,
wherein the pseudo-diode comprises a gate, a first terminal electrically connected to the gate of the pseudo-diode and to the second node, a second terminal electrically connected to the fourth voltage line, and a control electrode electrically connected to a fifth voltage line,
wherein the fifth voltage line is configured to transfer a control voltage from a power supply to the control electrode of the pseudo-diode, and
wherein the control voltage is configured to be adjusted such that a V-I curve of the pseudo-diode and a V-I curve of the light-emitting diode have similar shapes.