IP Library Granted Patent US 12,501,724
Granted Patent B2
US 12,501,724 · App. 18/429,727 · Granted Dec 16, 2025

Shallow trench textured regions and associated methods

Inventors: Homayoon Haddad (Beaverton, OR); Jutao Jiang (Tigard, OR)
Assignee: SiOnyx, LLC
H10F39/18B23K26/355B82Y40/00H10F39/014H10F39/026H10F39/199H10F39/806H10F39/8067H10F39/807H10F71/1221H10F77/122H10F77/413
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Quick Facts
Patent No.
US 12,501,724
App. No.
18/429,727
Granted
Dec 16, 2025
Kind
B2
Abstract

Photosensitive devices and associated methods are provided. In one aspect, for example, a photosensitive imager device can include a semiconductor layer having multiple doped regions forming a least one junction, a textured region coupled to the semiconductor layer and positioned to interact with electromagnetic radiation. The textured region can be formed from a series of shallow trench isolation features.

Claims (28)

1 . An optoelectronic photodiode device having enhanced absorption of electromagnetic radiation, comprising:

a semiconductor layer having one or more doped regions that form at least one junction;

a first textured region disposed on a light-incident surface of the semiconductor layer;

a second textured region disposed at a backside of the semiconductor layer and positioned to interact with electromagnetic radiation that passes through the semiconductor layer; and

a first bonding layer positioned between a support substrate and the second textured region.

2 . The device of claim 1 , wherein the first textured region comprises an array of pyramids.

3 . The device of claim 1 , wherein the first textured region comprises an array of inverted pyramids.

4 . The device of claim 1 , wherein the second textured region comprises shallow trench isolation features.

5 . The device of claim 1 , further comprising one or more deep trench isolation features configured to isolate the device.

6 . The device of claim 5 , wherein the one or more deep trench isolation features are configured to provide light trapping functionality.

7 . The device of claim 1 , wherein the backside of the semiconductor layer is coupled to the support substrate.

8 . The device of claim 7 , wherein the second textured region is positioned between the semiconductor layer and the support substrate.

9 . The device of claim 8 , further comprising a second bonding layer positioned between the first bonding layer and the support substrate.

10 . The device of claim 9 , further comprising a reflector layer disposed between the first bonding layer and the second bonding layer.

11 . The device of claim 1 , wherein one or more of the first textured region and the second textured region comprise surface features arranged according to a predetermined pattern.

12 . The device of claim 11 , wherein the predetermined pattern is a uniform grid arrangement.

13 . The device of claim 11 , wherein the predetermined pattern is a non-uniform arrangement.

14 . The device of claim 11 , wherein the surface features are uniform in height.

15 . The device of claim 1 , wherein the device is architecturally configured as a front-side illuminated device.

16 . A method of making an optoelectronic photodiode device having enhanced absorption of electromagnetic radiation, the method comprising:

doping a semiconductor layer to form at least one junction;

creating a first textured region on a light-incident surface of the semiconductor layer;

creating a second textured region on a backside of the semiconductor layer;

depositing a first bonding layer onto the backside of the semiconductor layer;

bonding a support substrate to the first bonding layer; and

forming one or more deep trench isolation features in the semiconductor layer, wherein the one or more deep trench isolation features are configured to provide light trapping functionality.

17 . The method of claim 16 , wherein the first textured region comprises an array of pyramids.

18 . The method of claim 16 , wherein the second textured region comprises shallow trench isolation features formed by etching, wherein the second textured region is positioned to interact with electromagnetic radiation that passes through the semiconductor layer.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 12, 2025
From: HADDAD, HOMAYOON; JIANG, JUTAO
To: SIONYX, INC.
Reel/Frame 072234/0252 →
CHANGE OF NAME Recorded Sep 12, 2025
From: SIONYX, INC.
To: SIONYX, LLC.
Reel/Frame 072872/0633 →
Continuity (7)
Continuation 17369384 · Jul 7, 2021
Continuation 16505283 · Jul 8, 2019
Continuation 15614256 · Jun 5, 2017
Continuation 14884181 · Oct 15, 2015
Continuation 14084392 · Nov 19, 2013
Provisional Application 61841326 · Jun 29, 2013
Related Publication 20240204033A1 · Jun 20, 2024
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