String based erase inhibit for one sided gate-induced drain leakage erase
A memory apparatus includes memory cells configured to store a threshold voltage and disposed in memory holes each defining a channel. The memory apparatus also includes a control means configured to apply a first erase voltage to the channel of each of the memory holes including the memory cells in a first loop of an erase operation. The control means verifies the threshold voltage of the memory cells being erased using a target erase verify level voltage and at least one high erase verify level voltage higher than the target erase verify level voltage. The control means slows erasing of ones of the memory cells in a second loop of the erase operation in response to the threshold voltage of the ones of the memory cells being erased being greater than the target erase verify level voltage and less than the at least one high erase verify level voltage.
1 . A memory apparatus, comprising:
memory cells configured to store a threshold voltage corresponding to one of a plurality of data states and disposed in memory holes each defining a channel, the channels being each connected to one of a plurality of bit lines; and
a control means configured to:
apply a first erase pulse of a plurality of erase pulses, the first erase pulse including an application of a first erase voltage to the bit lines of each of the memory holes including memory cells being erased in a first loop of an erase operation,
verify the threshold voltage of the memory cells being erased using a target erase verify level voltage and at least one high erase verify level voltage higher than the target erase verify level voltage, and
slow erasing of a first group of the memory cells being erased in a second loop of the erase operation in response to the threshold voltage of the first group of the memory cells being erased being greater than the target erase verify level voltage and less than the at least one high erase verify level voltage.
2 . The memory apparatus as set forth in claim 1 , wherein the control means is further configured to:
not slow erasing a second group of the memory cells being erased in the second loop of the erase operation in response to the threshold voltage of the ones the second group of the memory cells being erased being greater than the at least one high erase verify level voltage; and
completely inhibit erasing a third group of the memory cells being erased in the second loop of the erase operation in response to the threshold voltage of the third group of the memory cells being erased being less than the target erase verify level voltage.
3 . The memory apparatus as set forth in claim 1 , wherein the at least one high erase verify level voltage only includes a single high erase verify level voltage.
4 . The memory apparatus as set forth in claim 3 , wherein the control means is further configured to:
apply a second erase pulse, the second erase pulse including an application of a second erase voltage greater than the first erase voltage to a second group of the plurality of bit lines coupled to a second group of the memory cells having the threshold voltage greater than the single high erase verify level voltage in the second loop of the erase operation;
the second erase pulse further including an application of the second erase voltage minus a single quick pass erase voltage to a first group of the plurality of bit lines coupled to the first group of the memory cells having the threshold voltage less than the single high erase verify level voltage and greater than the target erase verify level voltage to slow erasing in the second loop of the erase operation; and
the second erase pulse further including an application of the second erase voltage minus an inhibit erase voltage to a third group of the plurality of bit lines coupled to a third group of the memory cells having the threshold voltage less than the target erase verify level voltage to completely inhibit erasing in the second loop of the erase operation.
5 . The memory apparatus as set forth in claim 1 , wherein the at least one high erase verify level voltage includes a first double high erase verify level voltage and a second double high erase verify level voltage greater in magnitude than the first double high erase verify level voltage.
6 . The memory apparatus as set forth in claim 5 , wherein the control means is further configured to:
apply a second erase pulse of the plurality of erase pulses, the second erase pulse including an application of a second erase voltage greater than the first erase voltage to a fourth group of the plurality of bit lines coupled to a fourth group of the memory cells having the threshold voltage greater than the second double high erase verify level voltage in the second loop of the erase operation;
the second erase pulse further including the application of the second erase voltage minus a first double quick pass erase voltage to a fifth group of the plurality of bit lines coupled to a fifth group of the memory cells having the threshold voltage less than the second double high erase verify level voltage and greater than the first double high erase verify level voltage to slow erasing at a first rate in the second loop of the erase operation;
the second erase pulse further including the application of the second erase voltage minus a second double quick pass erase voltage to a sixth group of the plurality of bit lines coupled to a sixth group of the memory cells having the threshold voltage less than the first double high erase verify level voltage and greater than the target erase verify level voltage to slow erasing at a second rate higher than the first rate in the second loop of the erase operation; and
the second erase pulse further including the application of the second erase voltage minus an inhibit erase voltage to a third group of the plurality of bit lines coupled to a third group of the memory cells having the threshold voltage less than the target erase verify level voltage to completely inhibit erasing in the second loop of the erase operation.
7 . The memory apparatus as set forth in claim 1 , wherein the memory holes are grouped into a plurality of strings and the control means is further configured to completely inhibit erasing of ones of the memory cells disposed in unselected ones of the plurality of strings not being erased during the erase operation.
8 . A controller in communication with a memory apparatus including memory cells configured to store a threshold voltage corresponding to one of a plurality of data states and disposed in memory holes each defining a channel, the channels being each connected to one of a plurality of bit lines, the controller configured to:
instruct the memory apparatus to apply a first erase pulse of a plurality of erase pulses, the first erase pulse including the application of a first erase voltage to the bit lines of each of the memory holes including memory cells being erased in a first loop of an erase operation;
instruct the memory apparatus to verify the threshold voltage of the memory cells being erased using a target erase verify level voltage and at least one high erase verify level voltage higher than the target erase verify level voltage; and
instruct the memory apparatus to slow erasing of a first group of the memory cells being erased in a second loop of the erase operation in response to the threshold voltage of the first group of the memory cells being erased being greater than the target erase verify level voltage and less than the at least one high erase verify level voltage.
9 . The controller as set forth in claim 8 , wherein the controller is further configured to:
instruct the memory apparatus to not slow erasing a second group of the memory cells being erased in the second loop of the erase operation in response to the threshold voltage of a second group of the memory cells being erased being greater than the at least one high erase verify level voltage; and
instruct the memory apparatus to completely inhibit erasing a third group of the memory cells being erased in the second loop of the erase operation in response to the threshold voltage of the third group of the memory cells being erased being less than the target erase verify level voltage.
10 . The controller as set forth in claim 8 , wherein the at least one high erase verify level voltage only includes a single high erase verify level voltage.
11 . The controller as set forth in claim 10 , wherein the controller is further configured to:
instruct the memory apparatus to apply a second erase pulse of the plurality of erase pulses, the second erase pulse including the application of a second erase voltage greater than the first erase voltage to a second group of the plurality of bit lines coupled to a second group of the memory cells having the threshold voltage greater than the single high erase verify level voltage in the second loop of the erase operation;
the second erase pulse also including the application of the second erase voltage minus a single quick pass erase voltage to a first group of the plurality of bit lines coupled to the first group of the memory cells having the threshold voltage less than the single high erase verify level voltage and greater than the target erase verify level voltage to slow erasing in the second loop of the erase operation; and
the second erase pulse also including the application of the second erase voltage minus an inhibit erase voltage to a third group of the plurality of bit lines coupled to a third group of the memory cells having the threshold voltage less than the target erase verify level voltage to completely inhibit erasing in the second loop of the erase operation.
12 . The controller as set forth in claim 8 , wherein the at least one high erase verify level voltage includes a first double high erase verify level voltage and a second double high erase verify level voltage greater in magnitude than the first double high erase verify level voltage.
13 . The controller as set forth in claim 12 , wherein the controller is further configured to:
instruct the memory apparatus to apply a second erase pulse of the plurality of erase pulses, the second erase pulse including an application of a second erase voltage greater than the first erase voltage to a fourth group of the plurality of bit lines coupled to a fourth group of the memory cells having the threshold voltage greater than the second double high erase verify level voltage in the second loop of the erase operation;
the second erase pulse further including the application of the second erase voltage minus a first double quick pass erase voltage to a fifth group of the plurality of bit lines coupled to a fifth group of the memory cells having the threshold voltage less than the second double high erase verify level voltage and greater than the first double high erase verify level voltage to slow erasing at a first rate in the second loop of the erase operation;
the second erase pulse further including the application of the second erase voltage minus a second double quick pass erase voltage to a sixth group of the plurality of bit lines coupled to a sixth group of the memory cells having the threshold voltage less than the first double high erase verify level voltage and greater than the target erase verify level voltage to slow erasing at a second rate higher than the first rate in the second loop of the erase operation; and
the second erase pulse further including the application of the second erase voltage minus an inhibit erase voltage to a third group of the plurality of bit lines coupled to a third group of the memory cells having the threshold voltage less than the target erase verify level voltage to completely inhibit erasing in the second loop of the erase operation.
14 . A method of operating a memory apparatus including memory cells configured to store a threshold voltage corresponding to one of a plurality of data states and disposed in memory holes each defining a channel, the channels being each connected to one of a plurality of bit lines; the method comprising the steps of:
applying a first erase pulse of a plurality of erase pulses, the first erase pulse including an application of a first erase voltage to the bit line of each of the memory holes including the memory cells being erased in a first loop of an erase operation;
verifying the threshold voltage of the memory cells being erased using a target erase verify level voltage and at least one high erase verify level voltage higher than the target erase verify level voltage; and
slowly erasing a first group of the memory cells being erased in a second loop of the erase operation in response to the threshold voltage of the first group of the memory cells being erased being greater than the target erase verify level voltage and less than the at least one high erase verify level voltage.
15 . The method as set forth in claim 14 , further including the steps of:
not slowly erasing a second group of the memory cells being erased in the second loop of the erase operation in response to the threshold voltage of a second group of the memory cells being erased being greater than the at least one high erase verify level voltage; and
completely inhibiting erasing a third group of the memory cells being erased in the second loop of the erase operation in response to the threshold voltage of a third group of the memory cells being erased being less than the target erase verify level voltage.
16 . The method as set forth in claim 14 , wherein the at least one high erase verify level voltage only includes a single high erase verify level voltage.
17 . The method as set forth in claim 16 , wherein the method further includes the steps of:
applying a second erase pulse of the plurality of erase pulses, the second erase pulse including an application of a second erase voltage greater than the first erase voltage to a second group of the plurality of bit lines coupled to a second group of the memory cells having the threshold voltage greater than the single high erase verify level voltage in the second loop of the erase operation;
the second erase pulse further including an application of the second erase voltage minus a single quick pass erase voltage to a first group of the plurality of bit lines coupled to the first group of the memory cells having the threshold voltage less than the single high erase verify level voltage and greater than the target erase verify level voltage to slow erasing in the second loop of the erase operation; and
the second erase pulse further including an application of the second erase voltage minus an inhibit erase voltage to a third group of the plurality of bit lines coupled to a third group of the memory cells having the threshold voltage less than the target erase verify level voltage to completely inhibit erasing in the second loop of the erase operation.
18 . The method as set forth in claim 14 , wherein the at least one high erase verify level voltage includes a first double high erase verify level voltage and a second double high erase verify level voltage greater in magnitude than the first double high erase verify level voltage.
19 . The method as set forth in claim 18 , wherein the method further includes the steps of:
applying a second erase pulse of the plurality of erase pulses, the second erase pulse including an application of a second erase voltage greater than the first erase voltage to a fourth group of the plurality of bit lines coupled to a fourth group of the memory cells having the threshold voltage greater than the second double high erase verify level voltage in the second loop of the erase operation;
the second erase pulse further including an application of the second erase voltage minus a first double quick pass erase voltage to a fifth group of the plurality of bit lines coupled to a fifth group of the memory cells having the threshold voltage less than the second double high erase verify level voltage and greater than the first double high erase verify level voltage to slow erasing at a first rate in the second loop of the erase operation;
the second erase pulse further including an application of the second erase voltage minus a second double quick pass erase voltage to a sixth group of the plurality of bit lines coupled to a sixth group of the memory cells having the threshold voltage less than the first double high erase verify level voltage and greater than the target erase verify level voltage to slow erasing at a second rate higher than the first rate in the second loop of the erase operation; and
the second erase pulse further including an application of the second erase voltage minus an inhibit erase voltage to a third group of the plurality of bit lines coupled to a third group of the memory cells having the threshold voltage less than the target erase verify level voltage to completely inhibit erasing in the second loop of the erase operation.
20 . The method as set forth in claim 14 , wherein the memory holes are grouped into a plurality of strings and the method further includes the step of completely inhibiting erasing of ones of the memory cells disposed in unselected ones of the plurality of strings not being erased during the erase operation.