Circuit devices with gate seals
View Patent ↗Various examples of a circuit device that includes gate stacks and gate seals are disclosed herein. In an example, a substrate is received that has a fin extending from the substrate. A placeholder gate is formed on the fin, and first and second gate seals are formed on sides of the placeholder gate. The placeholder gate is selectively removed to form a recess between side surfaces of the first gate seal and the second gate seal. A functional gate is formed within the recess and between the side surfaces of the first gate seal and the second gate seal.
1. A method comprising:
forming a fin-shaped active region protruding from a substrate;
depositing a placeholder gate material over the fin-shaped active region and the substrate;
patterning the placeholder gate material to form a placeholder gate structure directly over a channel region of the fin-shaped active region;
treating the placeholder gate structure to convert a portion of the placeholder gate structure into a dielectric layer, wherein the dielectric layer and a remaining portion of the placeholder gate structure have a same height;
forming a sidewall spacer along a sidewall surface of the dielectric layer; and
replacing the remaining portion of the placeholder gate structure with a functional gate stack.
2. The method of claim 1 , wherein the treating of the placeholder gate structure comprises performing a thermal oxidation to the placeholder gate structure.
3. The method of claim 1 , wherein the dielectric layer comprises polysilicon oxide.
4. The method of claim 1 , wherein the dielectric layer includes a conformal thickness along top and sidewall surfaces of the remaining portion of the placeholder gate structure.
5. The method of claim 1 , wherein a ratio of a thickness of the dielectric layer to a thickness of the placeholder gate structure is less than 1/10.
6. The method of claim 1 , wherein the forming of the sidewall spacer comprises:
after treating the placeholder gate structure, conformally depositing a gate spacer layer over the fin-shaped active region and the dielectric layer; and
selectively etching the gate spacer layer to remove portions of the gate spacer layer formed on horizontal surfaces of the fin-shaped active region and the dielectric layer.
7. The method of claim 1 , further comprising:
after the forming of the sidewall spacer, removing portions of the fin-shaped active region not directly covered by the placeholder gate structure, the dielectric layer, or the sidewall spacer to form source/drain recesses; and
forming source/drain features in the source/drain recesses.
8. The method of claim 1 , wherein the replacing of the remaining portion of the placeholder gate structure with the functional gate stack comprises:
selectively removing the remaining portion of the placeholder gate structure without etching the dielectric layer and the sidewall spacer to form a gate trench; and
forming the functional gate stack in the gate trench.
9. The method of claim 1 , further comprising:
forming a self-aligned capping layer on the functional gate stack, wherein a sidewall surface of the self-aligned capping layer is in direct contact with the dielectric layer.
10. A method comprising:
receiving a workpiece comprising a gate structure engaging a semiconductor fin;
forming a dielectric layer on top and sidewall surfaces of the gate structure, wherein the dielectric layer does not extend along a top surface of the semiconductor fin;
after the forming of the dielectric layer, conformally depositing a gate spacer layer over the workpiece; and
etching back the gate spacer layer and the dielectric layer to form a gate spacer and a gate seal layer, respectively, wherein the gate seal layer is disposed between the gate spacer and the gate structure.
11. The method of claim 10 , wherein the gate structure includes polysilicon and the gate seal layer includes polysilicon oxide.
12. The method of claim 10 , further comprising: after forming the gate spacer and the gate seal layer, replacing the gate structure with a functional gate stack comprising a high-K dielectric layer.
13. The method of claim 12 , wherein the high-K dielectric layer extends along an entire vertical surface of the gate seal layer.
14. The method of claim 10 , wherein the gate structure is isolated from the semiconductor fin by an interfacial layer, and the interfacial layer comprises silicon oxide.
15. The method of claim 10 , wherein the workpiece further comprises another semiconductor fin isolated from the semiconductor fin by an isolation feature, wherein the gate seal layer is in direct contact with the isolation feature.
16. A method comprising:
receiving a workpiece comprising a first semiconductor fin isolated from a second semiconductor fin by an isolation feature;
selectively forming an interfacial layer on the first semiconductor fin without forming the interfacial layer on the isolation feature;
forming a placeholder gate engaging the first semiconductor fin and having a first portion directly on the interfacial layer and a second portion directly on the isolation feature;
forming a dielectric layer extending along sidewall surfaces of the first portion and second portion of the placeholder gate;
conformally depositing a gate spacer layer over the workpiece, wherein the gate spacer layer is spaced apart from the first semiconductor fin by the interfacial layer;
etching back the gate spacer layer to removal horizontal portions of the gate spacer layer to form gate spacers extending along sidewall surfaces of the dielectric layer;
selectively removing the placeholder gate without etching the dielectric layer and the gate spacers to form a gate trench; and
forming a functional gate stack in the gate trench.
17. The method of claim 16 , wherein the dielectric layer further extends along a top surface of the placeholder gate, and the etching back of the gate spacer layer further removes a portion of the dielectric layer that extends along the top surface of the placeholder gate.
18. The method of claim 16 , wherein the dielectric layer is in direct contact with the isolation feature.
19. The method of claim 16 , wherein the etching back of the gate spacer layer further removes a portion of the interfacial layer not covered by the placeholder gate, the dielectric layer, or the gate spacers.
20. The method of claim 16 , wherein the gate spacer layer extends along and in direct contact with a top surface of the isolation feature.