LDMOS with enhanced safe operating area and method of manufacture
An integrated circuit comprising an n-type drift region, a gate structure directly on a first portion of the n-type drift region, a drain structure formed in a second portion of the n-type drift region, the gate structure and the drain structure being separated by a drift region length, a resist protective oxide (RPO) formed over a portion of the n-type drift region between the gate structure and the drain structure, a field plate contact providing a direct electrical connection to the resist protective oxide.
1. An integrated circuit comprising:
a gate structure;
a drain structure, wherein the gate structure and the drain structure are separated by a drift region, wherein the drift region has a drift region length (Lds);
a dielectric structure between the gate structure and the drain structure;
a first contact connected to the dielectric structure;
a second contact connected to the drain structure; and
a conductive pattern connected to both the first contact and the second contact.
2. The integrated circuit according to claim 1 , wherein:
the conductive pattern is configured to apply a drain voltage (Vdd) to both the first contact and the second contact.
3. The integrated circuit according to claim 1 , wherein:
the first contact is separated from the gate structure by a first distance, with the first distance being at least 35% of the Lds.
4. The integrated circuit according to claim 3 , wherein:
the first distance is between 40% and 70% of the Lds.
5. The integrated circuit according to claim 3 , wherein:
the first contact has a contact width, and
the contact width is between 10% and 30% of the Lds.
6. The integrated circuit according to claim 3 , wherein:
the Lds is at least 0.5 μm.
7. The integrated circuit according to claim 1 , wherein:
the first contact comprises a first paired contact having a first paired contact width and a second paired contact having a second paired contact width,
the first paired contact width is at least 10% of the Lds, and
the second paired contact width is at least 10% of the Lds.
8. The integrated circuit according to claim 1 , wherein:
the dielectric structure has a dielectric thickness, and
the dielectric thickness is at least 10% of the Lds.
9. The integrated circuit according to claim 1 , wherein:
the dielectric structure has a dielectric thickness; and
wherein the dielectric thickness is between 0.05 microns (μm) and 0.2 μm.
10. A method of manufacturing an integrated circuit comprising:
forming a gate structure on a substrate;
forming a drain structure;
forming a drift region in the substrate between the gate structure and the drain structure, wherein the drift region has a drift region length (Lds);
forming a dielectric structure between the gate structure and the drain structure, wherein the dielectric structure is over a portion of the drift region;
forming a first contact to the dielectric structure;
forming a second contact to the drain structure; and
forming a conductive pattern that connects the first contact to the second contact.
11. The method according to claim 10 , further comprising:
forming a sidewall structure adjacent the gate structure before forming the dielectric structure, wherein a vertical portion of the dielectric structure is formed adjacent the sidewall structure.
12. The method of claim 11 , further comprising:
extending a portion of the dielectric structure over a portion of an upper surface of the gate structure.
13. The method of claim 10 , further comprising:
extending the dielectric structure over the upper surface of the gate structure.
14. The method of claim 10 , further comprising:
defining a plurality of active areas on the substrate;
forming a field oxide structure between adjacent active areas; and
positioning the first contact closer to the drain structure than to the gate structure.
15. The method according to claim 10 , further comprising:
positioning the first contact on the dielectric structure at an offset distance from the gate structure, wherein the offset distance is between 40% and 70% of the Lds.
16. The method according to claim 10 , further comprising:
positioning the first contact on the dielectric structure at a contact point that is separated from the gate structure by at least 50% of the Lds.
17. The method according to claim 10 , further comprising:
forming a plurality of first contacts on the dielectric structure with each of the plurality of first contacts being separated from the gate structure by at least 40% of the Lds.
18. A method of improving high-voltage performance in a LDMOS integrated circuit comprising:
applying a predetermined voltage during device operation to both a dielectric plate over a portion of an n-type drift region and a drain structure, wherein the drain structure is adjacent a first end of the dielectric plate.
19. The method according to claim 18 , wherein:
the predetermined voltage is at least 14V.
20. The method of according to claim 18 , wherein:
the predetermined voltage is a drain voltage (Vdd) of the LDMOS integrated circuit.