IP Library Granted Patent US 12,642,013
Granted Patent B2
US 12,642,013 · App. 18/450,083 · Granted May 26, 2026

Wafer bonding process with reduced overlay distortion

Inventors: Christopher Michael Netzband (Albany, NY); Nathan Ip (Austin, TX)
Assignee: Tokyo Electron Limited
H10P10/128H10P72/78H10P74/203H10P95/906
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,642,013
App. No.
18/450,083
Granted
May 26, 2026
Kind
B2
Abstract

An embodiment method includes determining an upper vacuum condition, a lower vacuum condition, a bonding gap distance, and a striker pressure condition based on measuring residual distortions from a previously bonded wafer. The method includes applying the upper vacuum condition to an upper wafer using an upper wafer holder, the upper vacuum condition applied to a backside of the upper wafer, and the upper wafer having a front side being opposite of the backside. The method includes applying the lower vacuum condition to a lower wafer using a lower wafer holder. The method includes positioning the front side of the upper wafer over the front side of the lower wafer to create the bonding gap distance between the upper wafer and the lower wafer and striking the backside of the upper wafer with a striker using the striker pressure condition to bond the front side of the upper wafer and the front side of the lower wafer together.

Claims (52)

1 . A method comprising:

determining an upper vacuum condition, a lower vacuum condition, a bonding gap distance, and a striker pressure condition based on measuring residual distortions from a previously bonded wafer;

applying the upper vacuum condition to an upper wafer using an upper wafer holder by applying vacuum to a first vacuum surface area at a first vacuum level, the upper vacuum condition applied to a backside of the upper wafer, and the upper wafer having a front side being opposite of the backside, the first vacuum surface area being between 0.1% and 5% of a total area of the backside of the upper wafer, the first vacuum level being between 0 kPa and −100 kPa;

applying the lower vacuum condition to a lower wafer using a lower wafer holder by applying vacuum to a second vacuum surface area at a second vacuum level, the lower vacuum condition applied to a backside of the lower wafer, and the lower wafer having a front side being opposite of the backside, the second vacuum surface area being between 80% and 100% of a total area of the backside of the lower wafer, the second vacuum level being between 0 kPa and −100 kPa;

positioning the front side of the upper wafer over the front side of the lower wafer to create the bonding gap distance between the upper wafer and the lower wafer; and

striking the backside of the upper wafer with a striker using the striker pressure condition to bond the front side of the upper wafer and the front side of the lower wafer together.

2 . The method of claim 1 ,

wherein the striker pressure condition is between 10 kPa and 25 kPa; and

wherein the bonding gap distance is between 30 μm and 75 μm.

3 . The method of claim 1 , wherein the lower vacuum condition is less than-25 kPa.

4 . The method of claim 1 , further comprising performing an annealing process to strengthen the bond of the upper wafer and lower wafer, the annealing process comprising exposing the upper wafer and lower wafer to a temperature over 100° C. after the striking.

5 . A method comprising:

forming a first plurality of bonded wafers using a plurality of process recipes, the forming comprising, for each one of the first plurality of bonded wafers, striking a backside of a first wafer with a striker to bond the first wafer to a second wafer, each of the first plurality of bonded wafers being formed using a different one of the plurality of process recipes, the first wafer being held by an upper wafer holder by applying vacuum to a first vacuum surface area at a first vacuum level, the first vacuum surface area being between 0.1% and 5% of a total area of the backside of the first wafer, the first vacuum level being between 0 kPa and −100 kPa, the second wafer being held by a lower wafer holder by applying vacuum to a second vacuum surface area at a second vacuum level, the second vacuum surface area being between 80% and 100% of a total area of a backside of the second wafer, the second vacuum level being between 0 kPa and −100 kPa;

measuring overlay distortions for each of the first plurality of bonded wafers, and based thereon determining residual overlay distortions for each of the first plurality of bonded wafers;

selecting one of the first plurality of bonded wafers with a lower value of the residual overlay distortions;

determining a target process recipe associated with forming the selected one of the first plurality of bonded wafers; and

forming a second plurality of bonded wafers using the target process recipe.

6 . The method of claim 5 , wherein each one of the plurality of process recipes is different from another one of the plurality of process recipes in only one bonding parameter.

7 . The method of claim 5 , further comprising:

applying a first vacuum condition to the first wafer using the upper wafer holder, the first vacuum condition applied to the backside of the first wafer, and the first wafer having a front side being opposite of the backside;

applying a second vacuum condition to a second wafer using the lower wafer holder, the second vacuum condition applied to the backside of the second wafer, and the second wafer having a front side being opposite of the backside; and

positioning the front side of the second wafer over the front side of the first wafer to create a bonding gap distance between the first wafer and the second wafer, wherein the striking is performed at a striker pressure condition to bond the first wafer with the second wafer.

8 . The method of claim 7 , wherein each of the plurality of process recipes comprises the first vacuum condition, the second vacuum condition, the bonding gap distance, and the striker pressure condition.

9 . The method of claim 8 , wherein applying the first vacuum condition comprises

having a plurality of chuck vacuum zones, each having a vacuum level; and

activating a subset of chuck vacuum zones around the first wafer during the forming.

10 . The method of claim 8 , wherein applying the first vacuum condition comprises having a plurality of chuck vacuum zones, each having a vacuum level, wherein the vacuum level of adjacent ones of the chuck vacuum zones is different during the forming.

11 . The method of claim 7 , further comprising:

receiving, at a process controller, the target process recipe; and

based on the target process recipe, activating a plurality of chuck vacuum zones in the upper wafer holder and the lower wafer holder.

12 . The method of claim 7 , further comprising:

receiving, at a process controller, the target process recipe; and

based on the target process recipe, changing the striker pressure condition of the striker.

13 . The method of claim 7 , further comprising annealing the first plurality of bonded wafers, wherein the measuring overlay distortions is performed after the annealing.

14 . A method comprising:

forming a plurality of bonded wafers by performing a cycle of bonding, each cycle comprising:

receiving a wafer set to be bonded, the wafer set comprising a first wafer and a second wafer, the first wafer being held by a first wafer holder by applying vacuum to a first vacuum surface area at a first vacuum level, the first vacuum surface area being formed by activating a subset of chuck vacuum zones of the first wafer holder disposed around an outer edge of the first wafer, the second wafer being held by a second wafer holder by applying vacuum to a second vacuum surface area at a second vacuum level,

measuring an overlay distortion of a previous bonded wafer, and based thereon determining a residual overlay distortion of the previous bonded wafer,

determining a process recipe based on the previous residual overlay distortion,

positioning the first wafer to align with the second wafer and being separated by a bond gap distance, and

striking the backside of the first wafer with a striker to bond the first wafer and the second wafer together to form a bonded wafer.

15 . The method of claim 14 , wherein the striking comprises striking a central portion of the first wafer.

16 . The method of claim 14 , wherein the striking comprises striking a peripheral region of the first wafer.

17 . The method of claim 14 , wherein the measuring comprises scanning the previous bonded wafer with an infrared scanner and generating a distortion map.

18 . The method of claim 14 , wherein determining the process recipe comprises:

having a distortion model for the previous bonded wafer;

generating a residual distortion map from the residual overlay distortion; and

based on the distortion model, the process recipe, and the residual distortion map, select a new process recipe to minimize residual distortion, the new process recipe comprising a value for the bond gap distance and a pressure at which the striker strikes the first wafer.

19 . The method of claim 14 ,

wherein the process recipe comprises the first vacuum level and the second vacuum level.

20 . The method of claim 14 , wherein each cycle further comprises annealing the bonded wafer.

21 . The method of claim 14 , wherein the activated subset of chuck vacuum zones of the first wafer holder alternate with non-activated chuck vacuum zones around the outer edge of the first wafer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 16, 2023
From: NETZBAND, CHRISTOPHER MICHAEL; IP, NATHAN
To: TOKYO ELECTRON LIMITED
Reel/Frame 064613/0109 →
Continuity (2)
Provisional Application 63398495 · Aug 16, 2022
Related Publication 20240063022A1 · Feb 22, 2024
References Cited (13)
US 10438918B2 · Omori et al. · 2019 [cited by applicant]
US 10964563B2 · Wada et al. · 2021 [cited by applicant]
US 11721596B2 · Kohama · 2023 [cited by applicant]
US 11735465B2 · Sugakawa et al. · 2023 [cited by applicant]
US 20140113433A1 · Nguyen et al. · 2014 [cited by applicant]
US 20170178931A1 · Choi et al. · 2017 [cited by applicant]
US 20200273835A1 · Inamasu · 2020 [cited by applicant]
US 20200365442A1 · Sugakawa et al. · 2020 [cited by applicant]
US 20210050243A1 · Otsuka · 2021 [cited by applicant]
US 20220013416A1 · Ip · 2022 [cited by applicant]
US 20220187718A1 · Zach · 2022 [cited by examiner]
KR 20170070024A · 2017 [cited by applicant]
International Search Report and Written Opinion, International Application No. PCT/US2023/030245, dated Dec. 4, 2023, 10 pages. [cited by applicant]