IP Library › Granted Patent US 12,550,333
Granted Patent B2
US 12,550,333 · App. 18/453,483 · Granted Feb 10, 2026

Semiconductor switching devices having ferroelectric layers therein and methods of fabricating same

Inventors: Byounghoon Lee (Suwon-si, KR); Jongho Park (Suwon-si, KR); Musarrat Hasan (Sejong-si, KR); Wandon Kim (Seongnam-si, KR); Seungkeun Cha (Yongin-si, KR)
Assignee: Samsung Electronics Co., Ltd.
H10B51/30H10B51/00H10D30/701H10D64/681H10D64/689
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Quick Facts
Patent No.
US 12,550,333
App. No.
18/453,483
Granted
Feb 10, 2026
Kind
B2
Abstract

A semiconductor device includes a substrate, a channel on or in the substrate, a source/drain pair respectively on opposite ends of the channel, and a gate structure on the channel between the source/drain pair, wherein the gate structure includes an interfacial layer, a ferroelectric layer, a stabilization layer, an oxygen diffusion barrier layer, and a threshold voltage control layer that are sequentially stacked on the channel.

Claims (37)

1 . A method of manufacturing a semiconductor device, comprising:

forming an interfacial layer and a ferroelectric layer sequentially on a substrate;

forming a stabilization layer on the ferroelectric layer;

forming an oxygen diffusion barrier layer on the stabilization layer;

forming a silicon layer on the oxygen diffusion barrier layer; and

annealing the ferroelectric layer, wherein a thickness of the interfacial layer increases by 0 Å to 3 Å during the annealing of the ferroelectric layer.

2 . The method of claim 1 , wherein the stabilization layer comprises at least one material selected from a group consisting of TiN, MON, Mo, Al 2 O 3 , AIN, W, WN, WCN, La, LaO, LaN, TiAIN, and TION.

3 . The method of claim 2 , wherein the stabilization layer comprises MoN.

4 . The method of claim 1 , wherein the oxygen diffusion barrier layer comprises at least one material selected from a group consisting of TiN, AIN, TaN, TiSiN, TION, TiAIN, WCN, WN, and W.

5 . A method of manufacturing a semiconductor device, comprising:

forming an interfacial layer, a ferroelectric layer, a stabilization layer, and a sacrificial layer in sequence on a first region and a second region of a substrate;

annealing the ferroelectric layer;

removing the sacrificial layer;

removing a portion of the stabilization layer on the second region of the substrate;

forming a first threshold voltage control layer on the stabilization layer, on the first region of the substrate; and

forming a second threshold voltage control layer on a portion of the ferroelectric layer, on the second region of the substrate, wherein the stabilization layer is configured to stabilize a ferroelectric phase of the ferroelectric layer such that a ferroelectricity characteristic of the ferroelectric layer is preserved.

6 . The method of claim 5 , wherein a material included in the stabilization layer has a work function that is greater than a work function of a material included in the first threshold voltage control layer.

7 . The method of claim 5 , wherein a material included in the stabilization layer has a work function that is greater than a work function of the material included in the second threshold voltage control layer.

8 . The method of claim 5 , wherein:

forming the first threshold voltage control layer comprises forming a first lower threshold voltage control layer on the stabilization layer on the first region of the substrate and forming a first upper threshold voltage control layer on the first lower threshold voltage control layer, and

forming the second threshold voltage control layer comprises forming a second lower threshold voltage control layer on a portion of the ferroelectric layer on the second region of the substrate and forming a second upper threshold voltage control layer on the second lower threshold voltage control layer.

9 . The method of claim 8 , wherein a material included in the stabilization layer has a work function that is greater than a work function of a material included in the first lower threshold voltage control layer.

10 . The method of claim 8 , wherein a material included in the stabilization layer has a work function that is greater than a work function of the material included in the second lower threshold voltage control layer.

11 . The method of claim 8 , wherein a material included in the stabilization layer has a work function that is greater than a work function of a material included in the first upper threshold voltage control layer.

12 . The method of claim 8 , wherein a material included in the stabilization layer has a work function that is greater than a work function of a material included in the second upper threshold voltage control layer.

13 . The method of claim 8 , wherein a material included in the first lower threshold voltage control layer has a work function that is greater than a work function of a material included in the first upper threshold voltage control layer.

14 . The method of claim 8 , wherein a material included in the second lower threshold voltage control layer has a work function that is greater than a work function of a material included in the second upper threshold voltage control layer.

15 . The method of claim 8 , wherein the first lower threshold voltage control layer and the second lower threshold voltage control layer include a same material; and wherein the first lower threshold voltage control layer and the second lower threshold voltage control layer have different thicknesses from each other.

16 . The method of claim 8 , wherein the first upper threshold voltage control layer and the second lower threshold voltage control layer include a same material.

17 . The method of claim 5 , further comprising forming an oxygen diffusion barrier layer on the stabilization layer before forming the sacrificial layer.

18 . The method of claim 17 , further comprising removing a portion of the oxygen diffusion barrier layer on the second region of the substrate.

19 . A method of manufacturing a semiconductor device, comprising:

forming a channel region in or on a semiconductor substrate;

forming an interfacial layer, a ferroelectric layer, a stabilization layer, an oxygen diffusion barrier layer, and a sacrificial layer sequentially on the channel region;

annealing the ferroelectric layer;

removing the sacrificial layer; and

forming a threshold voltage control layer on the oxygen diffusion barrier layer, wherein the stabilization layer is configured to stabilize a ferroelectric phase of the ferroelectric layer such that a ferroelectricity characteristic of the ferroelectric layer is preserved.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 21, 2025
From: LEE, BYOUNGHOON; PARK, JONGHO; HASAN, MUSARRAT; KIM, WANDON; CHA, SEUNGKEUN
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 072994/0404 →
Priority Claims (1)
KR 10-2019-0092002 · Jul 29, 2019 · national
Continuity (3)
Continuation 17723523 · Apr 19, 2022
Continuation 16780006 · Feb 3, 2020
Related Publication 20230403861A1 · Dec 14, 2023
References Cited (28)
US 9269785B2 · Mueller et al. · 2016 [cited by applicant]
US 9349842B2 · Schloesser et al. · 2016 [cited by applicant]
US 9679893B2 · Yan et al. · 2017 [cited by applicant]
US 9768030B2 · Lee · 2017 [cited by applicant]
US 9793397B1 · Ando et al. · 2017 [cited by applicant]
US 10176859B2 · Duenkel et al. · 2019 [cited by applicant]
US 11038034B2 · Lee et al. · 2021 [cited by applicant]
US 20120315749A1 · Hempel et al. · 2012 [cited by applicant]
US 20150311206A1 · Hong et al. · 2015 [cited by applicant]
US 20150357429A1 · Dubourdieu et al. · 2015 [cited by applicant]
US 20160071947A1 · Wiatr et al. · 2016 [cited by applicant]
US 20160225867A1 · Kim · 2016 [cited by applicant]
US 20170125408A1 · Park et al. · 2017 [cited by applicant]
US 20170309488A1 · Sakai et al. · 2017 [cited by applicant]
US 20170358684A1 · Chen et al. · 2017 [cited by applicant]
US 20170365719A1 · Chen et al. · 2017 [cited by applicant]
US 20180269216A1 · Lee · 2018 [cited by applicant]
US 20180277550A1 · Yoo · 2018 [cited by applicant]
US 20190019875A1 · Tsai et al. · 2019 [cited by applicant]
US 20190057971A1 · Tsukamoto · 2019 [cited by applicant]
US 20190067488A1 · Tsai et al. · 2019 [cited by applicant]
US 20190164968A1 · Leib et al. · 2019 [cited by applicant]
US 20190333769A1 · Chen · 2019 [cited by examiner]
US 20200006547A1 · Hsu et al. · 2020 [cited by applicant]
US 20200013784A1 · An et al. · 2020 [cited by applicant]
US 20200013897A1 · Park et al. · 2020 [cited by applicant]
KR 100155866B1 · 1998 [cited by applicant]
US 10,164,094 B2, 12/2018, Tu et al. (withdrawn) [cited by applicant]