Differentiated voltage threshold metal gate structures for advanced integrated circuit structure fabrication

Inventors: Jeffrey S. Leib (Beaverton, OR); Jenny Hu (Santa Clara, CA); Anindya Dasgupta (Portland, OR); Michael L. Hattendorf (Portland, OR); Christopher P. Auth (Portland, OR)

Assignee: Intel Corporation

H01L29/66545 H01L21/02532 H01L21/02636 H01L21/0337 H01L21/28247 H01L21/28518 H01L21/28568 H01L21/3086 H01L21/31105 H01L21/31144 H01L21/76224 H01L21/76232 H01L21/76801 H01L21/76802 H01L21/76816 H01L21/76834 H01L21/76846 H01L21/76849 H01L21/76877 H01L21/76897 H01L21/823431 H01L21/823481 H01L21/823807 H01L21/823814 H01L21/823821 H01L21/823828 H01L21/823842 H01L21/823857 H01L21/823871 H01L21/823878 H01L23/528 H01L23/5226 H01L23/5283 H01L23/5329 H01L23/53209 H01L23/53238 H01L23/53266 H01L27/0207 H01L27/0886 H01L27/0922 H01L27/0924 H01L27/1104 H01L28/20 H01L28/24 H01L29/0649 H01L29/0653 H01L29/0847 H01L29/165 H01L29/167 H01L29/41783 H01L29/41791 H01L29/516 H01L29/6653 H01L29/6656 H01L29/66636 H01L29/66795 H01L29/66818 H01L29/785 H01L29/7843 H01L29/7845 H01L29/7846 H01L29/7848 H01L29/7851 H01L29/7854 H01L21/0217 H01L21/02164 H01L21/0332 H01L21/76883 H01L21/76885 H01L21/823437 H01L21/823475 H01L24/16 H01L24/32 H01L24/73 H01L29/665 H01L29/7842 H01L29/7853 H01L2224/16227 H01L2224/32225 H01L2224/73204

View Patent ↗

Loading inventors, assignments & file history…

Monitor This Case

Get email alerts when status or documents change.

Order Certified Copies

Most orders are placed with the USPTO same day — all within 24 business hours.

Order via The Patent Place →

Pre-filled with this patent's details

Quick Facts

Patent No.: US 10,741,669
App. No.: 15/859,355
Granted: Aug 11, 2020
Kind: B2

External Links

USPTO Patent Center↗ Full Patent PDF↗

Abstract

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. A gate dielectric layer is over a top of the fin and laterally adjacent sidewalls of the fin. An N-type gate electrode is over the gate dielectric layer over the top of the fin and laterally adjacent the sidewalls of the fin, the N-type gate electrode comprising a P-type metal layer on the gate dielectric layer, and an N-type metal layer on the P-type metal layer. A first N-type source or drain region is adjacent a first side of the gate electrode. A second N-type source or drain region is adjacent a second side of the gate electrode, the second side opposite the first side.

Claims (14)

1. An integrated circuit structure, comprising:

a first N-type device having a voltage threshold (VT), the first N-type device having a first gate dielectric layer, and a first N-type metal layer on the first gate dielectric layer, the first N-type device in or on a substrate, wherein the first N-type device has a channel region having a dopant concentration; and

a second N-type device having a voltage threshold (VT), the second N-type device having a second gate dielectric layer, a P-type metal layer on the second gate dielectric layer, and a second N-type metal layer on the P-type metal layer, the second N-type device in or on the substrate, wherein the second N-type device has a channel region having a dopant concentration, and wherein the dopant concentration of the channel region of the second N-type device is different than the dopant concentration of the channel region of the first N-type device.

2. The integrated circuit structure of claim 1 , wherein the VT of the second N-type device is higher than the VT of the first N-type device.

3. The integrated circuit structure of claim 1 , wherein the first N-type metal layer and the second N-type metal layer have a same composition.

4. The integrated circuit structure of claim 1 , wherein the first N-type metal layer and the second N-type metal layer have a same thickness.

5. The integrated circuit structure of claim 4 , wherein the first N-type metal layer and the second N-type metal layer have a same composition.

6. The integrated circuit structure of claim 1 , wherein the second N-type metal layer comprises titanium, aluminum, carbon and nitrogen, and the P-type metal layer comprises titanium and nitrogen.

7. The integrated circuit structure of claim 1 , further comprising:

a third N-type device having a voltage threshold (VT), the third N-type device having a third gate dielectric layer, and a third N-type metal layer on the third gate dielectric layer, wherein the VT of the third N-type device is different than the VT of the first N-type device, the third N-type device in or on the substrate.

8. The integrated circuit structure of claim 7 , wherein the third N-type device has a channel region having a dopant concentration, and wherein the dopant concentration of the channel region of the first N-type device is different than the dopant concentration of the channel region of the third N-type device.

9. The integrated circuit structure of claim 7 , wherein the first N-type metal layer and the third N-type metal layer have a same composition.

10. The integrated circuit structure of claim 7 , wherein the first N-type metal layer and the third N-type metal layer have a same thickness.

11. The integrated circuit structure of claim 7 , wherein the first N-type metal layer and the third N-type metal layer have a same composition and have a same thickness.

Assignments (1)

ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 23, 2018

From: LEIB, JEFFREY S.; HU, JENNY; DUSGUPTA, ANINDYA; HATTENDORF, MICHAEL L.; AUTH, CHRISTOPHER P.

To: INTEL CORPORATION

Reel/Frame 046946/0001 →

Continuity (2)

Provisional Application 62593149 · Nov 30, 2017

Related Publication 20190164968A1 · May 30, 2019

Cited By (4)

US 12,199,167 US 12,316,276 US 12,324,230 US 12,628,432