Semiconductor device
A semiconductor device includes peripheral active patterns on a substrate, first and second peripheral trench regions adjacent the peripheral active patterns, a first isolation liner on inner surfaces of the first and second peripheral trench regions, a second isolation liner on the first isolation liner in the first and second peripheral trench regions, and a device isolation layer on the second isolation liner in the first and second peripheral trench regions. The device isolation layer includes a seam therein in the second peripheral trench region. A width of the first peripheral trench region is greater than a width of the second peripheral trench region at a first height corresponding to top surfaces of the peripheral active patterns with respect to the substrate.
1 . A semiconductor device comprising:
a substrate including a cell region and a peripheral region;
peripheral active patterns on the peripheral region on the substrate;
peripheral word lines on the peripheral active patterns;
a word line positioned on the cell region;
a bit line positioned on the cell region and extending in a direction intersecting the word line;
a first peripheral trench region and a second peripheral trench region which are adjacent the peripheral active patterns;
a first isolation liner on inner surfaces of the first and second peripheral trench regions;
a second isolation liner on the first isolation liner in the first and second peripheral trench regions; and
a device isolation layer on the second isolation liner in the first and second peripheral trench regions,
wherein the device isolation layer includes a seam therein in the second peripheral trench region, and
wherein a width of the first peripheral trench region is greater than a width of the second peripheral trench region at a first height corresponding to top surfaces of the peripheral active patterns with respect to the substrate.
2 . The semiconductor device of claim 1 , wherein the device isolation layer includes at least one of silicon oxide or silicon nitride.
3 . The semiconductor device of claim 1 , wherein the first isolation liner is conformally on the inner surfaces of the first and second peripheral trench regions, and
wherein the second isolation liner is conformally on the first isolation liner in the first and second peripheral trench regions.
4 . The semiconductor device of claim 1 , wherein the first isolation liner and the second isolation liner include different materials.
5 . The semiconductor device of claim 1 , wherein a portion of the device isolation layer that is in the first peripheral trench region comprises a continuous portion that is free of a seam therein.
6 . The semiconductor device of claim 1 , wherein the device isolation layer includes a first device isolation layer and a second device isolation layer,
wherein the first device isolation layer is on the second isolation liner in the first peripheral trench region and is in the second peripheral trench region, and
wherein the second device isolation layer is in the first peripheral trench region.
7 . The semiconductor device of claim 6 , wherein the first device isolation layer and the second device isolation layer are integrated without an interface therebetween.
8 . The semiconductor device of claim 1 , further comprising:
a third peripheral trench region between ones of the peripheral active patterns,
wherein the first isolation liner further is on an inner surface of the third peripheral trench region, and
wherein the second isolation liner is in the third peripheral trench region on the first isolation liner.
9 . The semiconductor device of claim 8 , wherein a width of the third peripheral trench region is less than the width of the second peripheral trench region at the first height.
10 . The semiconductor device of claim 8 , wherein the device isolation layer does not extend into the third peripheral trench region.
11 . A semiconductor device comprising:
a substrate including a cell region and a peripheral region;
peripheral active patterns on the peripheral region on the substrate;
peripheral word lines on the peripheral active patterns;
a word line positioned on the cell region;
a bit line positioned on the cell region and extending in a direction intersecting the word line;
a first peripheral trench region and a second peripheral trench region adjacent the peripheral active patterns;
a first isolation liner on inner surfaces of the first and second peripheral trench regions;
a second isolation liner on the first isolation liner in the first and second peripheral trench regions;
a first device isolation layer on the second isolation liner in the first peripheral trench region and in the second peripheral trench region; and
a second device isolation layer in the first peripheral trench region.
12 . The semiconductor device of claim 11 , wherein the first device isolation layer includes a seam therein in the second peripheral trench region.
13 . The semiconductor device of claim 11 , wherein the second device isolation layer is continuous and is free of a seam therein.
14 . The semiconductor device of claim 11 , wherein the second device isolation layer does not extend into the second peripheral trench region.
15 . The semiconductor device of claim 11 , wherein the first device isolation layer includes at least one of silicon oxide or silicon nitride.
16 . A semiconductor device comprising:
a substrate including a cell region and a peripheral region;
a cell active pattern on the cell region, the cell active pattern including a center portion and an edge portion;
a word line intersecting the cell active pattern;
a bit line on the center portion of the cell active pattern and that extends in a direction intersecting the word line;
a storage node contact on the edge portion of the cell active pattern;
a landing pad on the storage node contact;
a data storage pattern on the landing pad;
peripheral active patterns on the peripheral region;
peripheral word lines on the peripheral active patterns;
a first peripheral trench region and a second peripheral trench region adjacent the peripheral active patterns;
a first isolation liner on inner surfaces of the first and second peripheral trench regions;
a second isolation liner on the first isolation liner in the first and second peripheral trench regions; and
a device isolation layer on the second isolation liner in the first and second peripheral trench regions,
wherein the device isolation layer includes a seam therein in the second peripheral trench region, and
wherein a width of the first peripheral trench region is greater than a width of the second peripheral trench region at a first height corresponding to top surfaces of the peripheral active patterns with respect to the substrate.
17 . The semiconductor device of claim 16 , wherein the substrate further includes a boundary region between the cell region and the peripheral region, and wherein the semiconductor device further comprises:
a boundary trench region on the boundary region between the cell active pattern and the peripheral active patterns,
wherein the first isolation liner and the second isolation liner sequentially overlap an inner surface of the boundary trench region, and
wherein the device isolation layer is in the boundary trench region on the second isolation liner.
18 . The semiconductor device of claim 17 , wherein a width of the boundary trench region is greater than the width of the second peripheral trench region at the first height.
19 . The semiconductor device of claim 17 , wherein the device isolation layer is continuous and is free of a seam therein in the boundary trench region.
20 . The semiconductor device of claim 16 , further comprising:
a cell trench region adjacent the cell active pattern,
wherein the device isolation layer does not extend into the cell trench region.