IP Library › Granted Patent US 12,733,246
Granted Patent B2
US 12,733,246 · App. 18/463,237 · Granted Sep 8, 2026

Semiconductor device

Inventors: Shunsuke Asaba (Himeji Hyogo, JP); Hiroshi Kono (Himeji Hyogo, JP)
Assignees: Kabushiki Kaisha Toshiba; Toshiba Electronic Devices & Storage Corporation
H10D84/146H10D62/127H10D62/8325
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,733,246
App. No.
18/463,237
Granted
Sep 8, 2026
Kind
B2
Abstract

A semiconductor device includes a first electrode, a first semiconductor layer connected to the first electrode and being of a first conductivity type, second semiconductor layers located on a portion of the first semiconductor layer and being of a second conductivity type, a third semiconductor layer located on a portion of the second semiconductor layer and being of the first conductivity type, a fourth semiconductor layer located in a portion of the first semiconductor layer between the second semiconductor layers and being of the second conductivity type, a second electrode facing the second semiconductor layer via an insulating film, and a third electrode connected to the second and third semiconductor layers. The first, second, third, and fourth semiconductor layers include silicon and carbon.

Claims (52)

1 . A semiconductor device, comprising:

a first electrode;

a first semiconductor layer connected to the first electrode, the first semiconductor layer including silicon and carbon, the first semiconductor layer being of a first conductivity type;

a plurality of second semiconductor layers located on a portion of the first semiconductor layer, the plurality of second semiconductor layers including silicon and carbon, the plurality of second semiconductor layers being of a second conductivity type;

a third semiconductor layer located on a portion of the second semiconductor layer, the third semiconductor layer including silicon and carbon, the third semiconductor layer being of the first conductivity type;

a fourth semiconductor layer located in a portion of the first semiconductor layer between the second semiconductor layers, the fourth semiconductor layer including silicon and carbon, the fourth semiconductor layer being of the second conductivity type;

a second electrode facing the second semiconductor layer via an insulating film;

a third electrode connected to the second and third semiconductor layers;

a conductive layer having an ohmic connection with the second semiconductor layer, the third semiconductor layer, and the third electrode; and

a metal layer located on the first semiconductor layer, the metal layer having a Schottky junction with the first semiconductor layer, wherein

the second semiconductor layer extends in a first direction,

a plurality of first openings is arranged along the first direction in the second semiconductor layer,

the third semiconductor layer extends in the first direction,

a second opening and a third opening are alternately arranged along the first direction in the third semiconductor layer,

the conductive layer is located in the second opening, and

the metal layer is located in the third opening and contacts a portion of the first semiconductor layer located in the first opening.

2 . The device according to claim 1 , wherein

the metal layer and the conductive layer are alternately arranged along a second direction crossing the first direction.

3 . The device according to claim 1 , wherein

the first semiconductor layer is interposed between the conductive layer and the fourth semiconductor layer.

4 . The device according to claim 1 , wherein

the first semiconductor layer is interposed between the metal layer and the fourth semiconductor layer.

5 . The device according to claim 1 , wherein

the fourth semiconductor layer is separated from an upper surface of the first semiconductor layer.

6 . The device according to claim 1 , wherein

the fourth semiconductor layer contacts the second semiconductor layer.

7 . A semiconductor device, comprising:

a first electrode;

a first semiconductor layer connected to the first electrode, the first semiconductor layer including silicon and carbon, the first semiconductor layer being of a first conductivity type;

a plurality of second semiconductor layers located on a portion of the first semiconductor layer, the plurality of second semiconductor layers including silicon and carbon, the plurality of second semiconductor layers being of a second conductivity type;

a third semiconductor layer located on a portion of the second semiconductor layer, the third semiconductor layer including silicon and carbon, the third semiconductor layer being of the first conductivity type;

a fourth semiconductor layer located in a portion of the first semiconductor layer between the second semiconductor layers, the fourth semiconductor layer including silicon and carbon, the fourth semiconductor layer being of the second conductivity type;

a second electrode facing the second semiconductor layer via an insulating film; and

a third electrode connected to the second and third semiconductor layers, wherein

an upper surface of the fourth semiconductor layer is positioned lower than an upper surface of the second semiconductor layer, and

a lower surface of the fourth semiconductor layer is positioned higher than a lower surface of the second semiconductor layer.

8 . The device according to claim 1 , wherein

the metal layer includes titanium.

9 . The device according to claim 1 , wherein

the conductive layer includes nickel and silicon.

10 . A semiconductor device, comprising:

a first electrode;

a first semiconductor layer connected to the first electrode, the first semiconductor layer being of a first conductivity type;

a second semiconductor layer located on a portion of the first semiconductor layer, the second semiconductor layer being of a second conductivity type;

a third semiconductor layer located on a portion of the second semiconductor layer, the third semiconductor layer being of the first conductivity type;

a fourth semiconductor layer located on a side surface of the second semiconductor layer in the first semiconductor layer, the fourth semiconductor layer being of the second conductivity type;

a second electrode located in a region including a region directly above the fourth semiconductor layer, the second electrode facing the second semiconductor layer; and

a third electrode connected to the second and third semiconductor layers, wherein

an upper surface of the fourth semiconductor layer is positioned lower than an upper surface of the second semiconductor layer, and

a lower surface of the fourth semiconductor layer is positioned higher than a lower surface of the second semiconductor layer.

11 . The device according to claim 10 , wherein

the first semiconductor layer, the second semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer include silicon and carbon.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 7, 2023
From: ASABA, SHUNSUKE; KONO, HIROSHI
To: KABUSHIKI KAISHA TOSHIBA; TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
Reel/Frame 064835/0853 →
Priority Claims (1)
JP 2023-041976 · Mar 16, 2023 · national
Continuity (1)
Related Publication 20240313107A1 · Sep 19, 2024
References Cited (26)
US 9786778B1 · Morizuka · 2017 [cited by applicant]
US 11502173B2 · Shimizu · 2022 [cited by applicant]
US 11527615B2 · Suto et al. · 2022 [cited by applicant]
US 11527661B2 · Irifune et al. · 2022 [cited by applicant]
US 20040099905A1 · Baliga · 2004 [cited by examiner]
US 20100096692A1 · Saito · 2010 [cited by examiner]
US 20100155836A1 · Hebert · 2010 [cited by examiner]
US 20110057202A1 · Kono · 2011 [cited by applicant]
US 20140367771A1 · Chatty · 2014 [cited by applicant]
US 20170077272A1 · Kubo · 2017 [cited by examiner]
US 20170271324A1 · Kumagai · 2017 [cited by examiner]
US 20220013663A1 · Kawahara et al. · 2022 [cited by applicant]
US 20220271155A1 · Kono · 2022 [cited by applicant]
US 20230022394A1 · Sdrulla · 2023 [cited by applicant]
US 20230036221A1 · Hino et al. · 2023 [cited by applicant]
JP 2011060930A · 2011 [cited by applicant]
JP 6649183B2 · 2020 [cited by applicant]
JP 2021002652A · 2021 [cited by applicant]
JP 2021077774A · 2021 [cited by applicant]
JP 2022030298A · 2022 [cited by applicant]
JP 2022051424A · 2022 [cited by applicant]
JP 2022130063A · 2022 [cited by applicant]
WO 2020110285A1 · 2020 [cited by applicant]
WO 2021161436A1 · 2021 [cited by applicant]
WO 2023009325A1 · 2023 [cited by applicant]
Notice of Reasons for Refusal mailed Feb. 16, 2026 in corresponding Japanese Patent Application No. 2023-041976, 10 pages (with Translation). [cited by applicant]