IP Library Granted Patent US 12,135,887
Granted Patent B2
US 12,135,887 · App. 18/464,630 · Granted Nov 5, 2024

Sequential data optimized sub-regions in storage devices

Inventors: David Aaron Palmer (Boise, ID); Sean L Manion (Boise, ID); Jonathan Scott Parry (Boise, ID); Stephen Hanna (Fort Collins, CO); Qing Liang (Boise, ID); Nadav Grosz (Broomfield, CO); Christian M. Gyllenskog (Meridian, ID); Kulachet Tanpairoj (Santa Clara, CA)
G06F3/0631G06F3/061G06F3/0679G06F12/0246G06F2212/7201G06F2212/7204
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Quick Facts
Patent No.
US 12,135,887
App. No.
18/464,630
Granted
Nov 5, 2024
Kind
B2
Abstract

Apparatus and methods are disclosed, including using a memory controller to partition a memory array into a first portion and a second portion, the first portion and second portion having non-overlapping logical block addressing (LBA) ranges. The memory controller assigns a first granularity of a first logical-to-physical (L2P) mapping table entry for the first portion of the memory array designated for a first usage, and a second granularity of a second L2P mapping table entry for the second portion of the memory array designated for a second usage, where the second granularity is not equal to the first granularity. The memory controller stores the first granularity and the second granularity in the memory array, and stores at least a portion of the first L2P mapping table entry and the second L2P mapping table entry in an L2P cache of the memory controller.

Claims (33)

1. A storage system, comprising:

memory; and

a controller configured to perform operations including:

partitioning the memory into a plurality of portions having non-overlapping logical block addressing (LBA) ranges; and

assigning a respective performance level to a respective logical-to-physical (L2P) mapping table entry for each of the plurality of portions of the memory, wherein at least two of the performance levels are different from each other, and wherein the respective L2P mapping table entry comprises a respective granularity.

2. The storage system of claim 1 , wherein at least a portion of the L2P mapping table entries is stored in an L2P cache of the controller.

3. The storage system of claim 1 , wherein the respective performance level is assigned based on a respective designated usage of each of the plurality of portions of the memory.

4. The storage system of claim 3 , wherein the plurality of portions of memory comprises a plurality of types of memory operated at different speeds.

5. The storage system of claim 1 , wherein the plurality of portions comprises a first portion having a first granularity larger than a second granularity of a second portion of the plurality of portions.

6. The storage system of claim 5 , wherein a first write performance corresponding to the first granularity is less than a second write performance corresponding to the second granularity.

7. The storage system of claim 6 , wherein a first read performance corresponding to the first granularity is better than a second read performance corresponding to the second granularity.

8. The storage system of claim 7 , wherein the first portion has a better sequential write performance than the second portion.

9. The storage system of claim 1 , wherein the storage system comprises a NAND storage device.

10. A method, comprising:

partitioning, by a controller of a storage system, memory of the storage system into a plurality of portions having non-overlapping logical block addressing (LBA) ranges;

assigning, by the controller, a respective performance level to a respective logical-to-physical (L2P) mapping table entry for each of the plurality of portions of the memory, wherein at least two of the performance levels are different from each other; and

assigning, by the controller, a respective granularity to the respective L2P mapping table entry.

11. The method of claim 10 , wherein the respective performance level is assigned based on a respective designated usage of each of the plurality of portions of the memory.

12. The method of claim 10 , further comprising:

storing the respective granularity in the memory.

13. The method of claim 12 , further comprising:

storing at least a portion of the L2P mapping table entries in an L2P cache of the controller.

14. The method of claim 12 , wherein the plurality of portions comprises a first portion having a first granularity larger than a second granularity of a second portion of the plurality of portions.

15. The method of claim 14 , wherein the first portion has a better sequential write performance than the second portion.

16. A tangible non-transitory machine readable storage medium configured to store instructions, which when executed by a controller of a storage system, cause the controller to:

partition memory of the storage system into a plurality of portions having non-overlapping logical block addressing (LBA) ranges;

assign a respective performance level to a respective logical-to-physical (L2P) mapping table entry for each of the plurality of portions of the memory, wherein at least two of the performance levels are different from each other; and

assign a respective granularity to the respective L2P mapping table entry.

17. The tangible non-transitory machine readable storage medium of claim 16 , wherein the storage system comprises a NAND storage device.

18. The tangible non-transitory machine readable storage medium of claim 16 , wherein the instructions further cause the controller to:

store the respective granularity in the memory; and

store at least a portion of the L2P mapping table entries in an L2P cache of the controller.

19. The tangible non-transitory machine readable storage medium of claim 18 , wherein the plurality of portions comprises a first portion having a first granularity larger than a second granularity of a second portion of the plurality of portions, and wherein the first portion has a better sequential write performance than the second portion.

Continuity (4)
Continuation 17702217 · Mar 23, 2022
Continuation 17129087 · Dec 21, 2020
Continuation 16237134 · Dec 31, 2018
Related Publication 20240020033A1 · Jan 18, 2024