Apparatuses comprising transistors including extension regions
Methods of forming a transistor might include forming a dielectric overlying a semiconductor having a first conductivity type, forming a conductor overlying the dielectric, patterning the conductor and dielectric to define a gate stack of the transistor, forming a first extension region base and a second extension region base in the semiconductor, forming a first extension region riser overlying the first extension region base and forming a second extension region riser overlying the second extension region base, and forming a first source/drain region in the first extension region riser and forming a second source/drain region in the second extension region riser, wherein the first extension region base, the second extension region base, the first source/drain region, and the second source/drain region each have a second conductivity type different than the first conductivity type.
1. An apparatus, comprising:
gate stacks of transistors vertically overlying a semiconductive structure;
extension regions comprising horizontally extending portions within the semiconductive structure and in contact with at least a portion of a dielectric material of the transistors, and vertically extending portions vertically overlying the horizontally extending portions; and
source/drain regions within the vertically extending portions of the extension regions, lower boundaries of the source/drain regions vertically elevated above upper boundaries of the gate stacks.
2. The apparatus of claim 1 , wherein upper surfaces of the horizontally extending portions of the extension regions and an upper surface of the semiconductive structure are substantially coplanar with one another, upper surfaces of the vertically extending portions of the extension regions vertically elevated relative to the upper surface of the semiconductive structure.
3. The apparatus of claim 1 , wherein lower surfaces of the vertically extending portions of the extension regions directly physically contact upper surfaces of the horizontally extending portions thereof.
4. The apparatus of claim 1 , wherein:
a conductivity type of the source/drain regions is substantially the same as an additional conductivity type of the extension regions; and
the additional conductivity type of the extension regions differs from a further conductivity type of the semiconductive structure.
5. The apparatus of claim 1 , wherein a conductivity level of the extension regions differs from a conductivity level of the source/drain regions.
6. The apparatus of claim 1 , further comprising isolation structures within the semiconductive structure, wherein upper surfaces of the isolation structures are substantially coplanar with upper surfaces of the horizontally extending portions of the extension regions and vertically recessed relative to upper surfaces of the vertically extending portions thereof.
7. The apparatus of claim 6 , wherein lateral side surfaces of the vertically extending portions of the extension regions are substantially aligned with lateral side surfaces of the isolation structures.
8. An apparatus, comprising:
gate stacks of transistors vertically overlying a semiconductive material;
first extension regions within the semiconductive material, the first extension regions extending horizontally toward the gate stacks and terminating beyond one edge of dielectric material of the gate stacks;
second extension regions vertically overlying the first extension regions and extending beyond upper surfaces of the semiconductive material;
source/drain regions within the second extension regions, the source/drain regions comprising a different material composition than the second extension regions, wherein lower boundaries of the source/drain regions are vertically elevated above upper boundaries of the gate stacks; and
contacts coupled to the source/drain regions.
9. The apparatus of claim 8 , wherein an entirety of the contacts are at an elevation above upper surfaces of the gate stacks of the transistors.
10. The apparatus of claim 8 , wherein a material composition of the first extension regions is substantially the same as a material composition of the second extension regions.
11. The apparatus of claim 8 , wherein the semiconductive material comprises a different dopant species than the first extension regions and the second extension regions.
12. The apparatus of claim 8 , wherein a conductivity level of the second extension regions differs from a conductivity level of the first extension regions.
13. The apparatus of claim 8 , wherein a single second extension region intervenes between two laterally adjacent gate stacks of the transistors.
14. The apparatus of claim 8 , wherein an individual gate stack of the transistors is horizontally adjacent to opposing portions of the second extension regions, a distance between one of the opposing portions and the individual gate stack relatively greater than an additional distance between the other of the opposing portions and the individual gate stack.
15. An apparatus, comprising:
semiconductive material comprising a first conductivity type;
gate stacks of transistors vertically overlying the semiconductive material;
extension regions comprising a second conductivity type differing from the first conductivity type, the extension regions comprising:
extension region bases positioned within the semiconductive material and extending horizontally beyond one edge of the dielectric material of the transistors; and
extension region risers overlying the extension region bases;
source/drain regions comprising the second conductivity type vertically overlying and spaced from the semiconductive material, the source/drain regions in communication with the extension regions, wherein lower boundaries of the source/drain regions are vertically elevated above upper boundaries of the gate stacks; and
contact structures adjacent to the source/drain regions, a width of the contact structures relatively less than an additional width of the source/drain regions in at least one horizontal direction.
16. The apparatus of claim 15 , wherein upper portions of the extension region risers of the extension regions comprising the source/drain regions.
17. The apparatus of claim 16 , wherein a conductivity level of the source/drain regions is relatively greater than conductivity levels of the extension regions.
18. The apparatus of claim 16 , wherein the extension region risers directly vertically intervene between the source/drain regions and the extension region bases.
19. The apparatus of claim 15 , wherein a lateral extent of the extension region bases differs from a lateral extent of the extension region risers.
20. The apparatus of claim 15 , wherein portions of the conductive material of the gate structures are in vertical alignment with the extension region risers of the extension regions.