Replacement gate MOSFET with raised source and drain
A disposable dielectric spacer is formed on sidewalls of a disposable material stack. Raised source/drain regions are formed on planar source/drain regions by selective epitaxy. The disposable dielectric spacer is removed to expose portions of a semiconductor layer between the disposable material stack and the source/drain regions including the raised source/drain regions. Dopant ions are implanted to form source/drain extension regions in the exposed portions of the semiconductor layer. A gate-level dielectric layer is deposited and planarized. The disposable material stack is removed and a gate stack including a gate dielectric and a gate electrode fill a cavity formed by removal of the disposable material stack. Optionally, an inner dielectric spacer may be formed on sidewalls of the gate-level dielectric layer within the cavity prior to formation of the gate stack to tailor a gate length of a field effect transistor.
1. A semiconductor structure comprising a field effect transistor located on a semiconductor substrate, said field effect transistor comprising:
a semiconductor portion including a body region, source/drain extension regions laterally contacting said body region, and planar source/drain regions laterally contacting said source/drain extension regions and having a same type of doping as said source/drain extension regions;
a gate stack, from bottom to top, of a gate dielectric and a gate conductor, wherein said gate stack contacts said body region and a portion of each of said source/drain extension regions;
raised source/drain regions having a same type of doping as said source/drain extension regions, wherein each of said raised source/drain regions contacts a top surface of said planar source/drain regions and is laterally spaced from said gate stack by a same distance; and
a gate-level dielectric layer contacting top surfaces of said source/drain extension region, top surfaces of said planar source/drain region, and top surfaces and sidewalls of said raised source/drain regions.
2. The semiconductor structure of claim 1 , wherein said gate-level dielectric layer further contacts sidewalls of said gate dielectric.
3. The semiconductor structure of claim 1 , further comprising a dielectric gate spacer laterally contacting said gate dielectric, wherein outer sidewalls of said dielectric gate spacer are vertical.
4. The semiconductor structure of claim 3 , wherein said gate-level dielectric layer contacts said outer sidewalls of said dielectric gate spacer.
5. The semiconductor structure of claim 1 , wherein said raised source/drain regions are epitaxially aligned to said planar source/drain regions.
6. The semiconductor structure of claim 1 , wherein a top surface of said body region, top surfaces of said source/drain extension regions, and top surfaces of said planar source/drain regions are located within a same horizontal plane.
7. The semiconductor structure of claim 1 , wherein the raised source/drain regions have a thickness of 5 nm to 100 nm.
8. The semiconductor structure of claim 1 , wherein the body region includes an active region composed of a single crystal semiconductor material.
9. The semiconductor structure of claim 1 , wherein the body region is composed of a semiconductor material that is different from a semiconductor material for the raised source/drain regions.
10. The semiconductor structure of claim 1 , wherein the body region and the planar source/drain regions are composed of a semiconductor material having a same composition.
11. The semiconductor structure of claim 1 , wherein the planar source/drain regions have a greater dopant concentration than the source/drain extension regions.
12. The semiconductor structure of claim 1 , wherein a dopant concentration of the planar source/drain regions ranges from 3.0×10 20 /cm 3 to 3.0×10 21 /cm 3 , and a dopant concentration of the source/drain extension regions ranges from 1.0×10 19 /cm 3 to 3.0×10 20 /cm 3 .
13. The semiconductor structure of claim 1 , wherein the gate dielectric is selected from the group consisting of HfO 2 , ZrO 2 , La 2 O 3 , Al 2 O 3 , TiO 2 , SrTiO 3 , LaAlO 3 , Y 2 O 3 , HfO x N y , ZrO x N y , La 2 O x N y , Al 2 O x N y , TiO x N y , SrTiO x N y , LaAlO x N y , Y 2 O x N y , a silicate thereof, and a combination thereof, wherein a value of x is from about 0.5 to about 3 and each value of y is from 0 to about 2.
14. The semiconductor structure of claim 1 , wherein the gate dielectric has a thickness ranging from 1 nm to 6 nm.
15. The semiconductor structure of claim 1 , wherein the gate conductor comprises a work function metal portion.
16. The semiconductor structure of claim 14 , wherein the work function metal portion comprises a metal, a metal alloy, or a metallic nitride.
17. The semiconductor structure of claim 14 , wherein the work function metal portion comprises TaN, TiN, WN, TiAlN, TaCN or a combination thereof.