Circuit and method for testing a circuit
According to various embodiments, a circuit is described including a plurality of scan flip-flops including a sequence of scan flip-flops, wherein at least some scan flip-flops of the sequence are wrapper scan flip-flops, and including, for each scan flip-flop of at least a subset of the scan flip-flops, at the wrapper scan flip-flop's test input a respective test input circuit configured to, when supplied with a mode control signal having a first value, connect the test input to the output of the preceding wrapper scan flip-flop such that the test input of the flip-flop is supplied with the content of the preceding wrapper scan flip-flop and when supplied with the mode control signal having a second value, connect the test input to an output of a part of the circuit such that the test input of the flip-flop is supplied with a value depending on a test result.
1. A circuit, comprising:
a plurality of scan flip-flops including a sequence of scan flip-flops, wherein at least some scan flip-flops of the sequence of scan flip-flops are wrapper scan flip-flops, each scan flip-flop of the sequence of scan flip-flops having a D input, a test enable input, a test input and a data output,
wherein the circuit comprises, for each scan flip-flop of at least a subset of the scan flip-flops of the sequence of scan flip-flops, at the scan flip-flop's test input a respective test input circuit comprising a plurality of logic gates, wherein the plurality of logic gates of the test input circuit is configured to,
when supplied with a mode control signal having a first value indicating a shift mode, connect the test input to the output of the scan flip-flop preceding the scan flip-flop in the sequence such that the test input of the scan flip-flop is supplied with the content of the scan flip-flop preceding the scan flip-flop in the sequence and
when supplied with the mode control signal having a second value indicating a capture mode, connect the test input to an output of a subcircuit of the circuit, wherein the subcircuit is under test, such that the test input of the flip-flop is supplied with a value depending on a test result provided by the subcircuit.
2. The circuit of claim 1 , wherein the circuit is configured to, in the shift mode, mask the test result provided by the part of the circuit by the second value of the mode control signal.
3. The circuit of claim 1 , wherein the circuit is configured to, in the capture mode, combine the test result provided by the part of the circuit with the content of the scan flip-flop preceding the scan flip-flop in the sequence.
4. The circuit of claim 3 , wherein a combination of the test result and the content of the scan flip-flop comprises an XOR combination.
5. A method for testing a circuit according to claim 1 comprising:
generating a test pattern;
supplying the test pattern to the circuit;
supplying the mode control signal with the second value to the test input circuits of the scan flip-flops of the sub set;
capturing test results generated by the circuit in response to the test pattern by the sequence of scan flip-flops;
supplying the mode control signal with the first value to the test input circuits of the scan flip-flops of the sub set;
shifting the captured test results through the sequence of scan flip-flops to a test output pin of the circuit; and
evaluating the test results generated by the circuit in response to the test pattern.
6. The method of claim 5 , comprising supplying the test pattern to the circuit by supplying the mode control signal with the first value to the test input circuits of the scan flip-flops of the sub set and shifting the test pattern into the sequence of scan flip-flops.
7. The method of claim 5 , comprising supplying another test pattern to the circuit by the mode control signal with the first value the test input circuits of the scan flip-flops of the sub set and shifting the other test pattern into the sequence of scan flip-flops;
receiving test results generated by the circuit in response to the other test pattern; and
evaluating the test results generated by the circuit in response to the other test pattern.
8. The method of claim 5 , wherein the part of the circuit is a sub-circuit of the circuit and wherein the circuit comprises a further sequence of scan flip-flops, each scan flip-flop having a D input, a test enable input, a test input and a data output, wherein the circuit comprises, for each scan flip-flop of at least a subset of the scan flip-flops of the further sequence, at the scan flip-flop's test input a respective test input circuit configured to,
when supplied with a mode control signal having a first value, connect the test input to the output of the scan flip-flop preceding the scan flip-flop in the sequence such that the test input of the flip-flop is supplied with the content of the scan flip-flop preceding the scan flip-flop in the sequence;
when supplied with a mode control signal having a second value, connect the test input to an output of a further sub-circuit of the circuit such that the test input of the flip-flop is supplied with a value depending on a test result provided by the further sub-circuit;
wherein the test pattern is supplied to the circuit by supplying the first value to the test input circuits of the scan flip-flops of the subset of the scan flip-flops of the further sequence and shifting the test pattern into the further sequence of scan flip-flops.
9. The circuit of claim 1 , wherein the plurality of logic gates of the test input circuit comprises an OR-gate and an NXOR-gate.
10. The circuit of claim 9 , wherein a first input of the OR-gate is connected to an output of a circuit to be observed, and a second input of the OR-gate is connected to a scan enable line; wherein an output of the OR-gate is connected to a first input of the NXOR-gate, and a second input of the NXOR-gate is connected to an output of a proceeding wrapper scan flip-flop.