THREE-DIMENSIONAL MEMORY DEVICES INCLUDING SELF-ALIGNED SOURCE-CHANNEL JUNCTIONS AND METHODS FOR FORMING THE SAME
A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, a memory opening fill structure located in the memory opening and including a memory film, a vertical semiconductor channel, and a semiconductor source cap structure which is at least partially laterally surrounded by the memory film and which contacts the vertical semiconductor channel, and a source layer contacting at least a first end surface segment of the semiconductor source cap structure.
1 . A semiconductor structure, comprising:
an alternating stack of insulating layers and electrically conductive layers;
a memory opening vertically extending through the alternating stack;
a memory opening fill structure located in the memory opening and comprising a memory film, a vertical semiconductor channel, and a semiconductor source cap structure which is at least partially laterally surrounded by the memory film and which contacts the vertical semiconductor channel; and
a source layer contacting at least a first end surface segment of the semiconductor source cap structure.
2 . The semiconductor structure of claim 1 , further comprising a source-side spacer layer located between the source layer and the alternating stack, wherein:
the memory opening also vertically extends through the source-side spacer layer; and
the semiconductor source cap structure is laterally surrounded by the source-side spacer layer.
3 . The semiconductor structure of claim 2 , wherein:
the semiconductor source cap structure further comprises an annular conical surface segment adjoined to the first end surface segment; and
the annular conical surface segment is laterally surrounded by the memory film and by the source-side spacer layer.
4 . The semiconductor structure of claim 3 , wherein the annular conical surface segment comprises:
a first tapered annular area in contact with the source layer; and
a second tapered annular area in contact with the memory film.
5 . The semiconductor structure of claim 3 , wherein the semiconductor source cap structure further comprises a second end surface segment that contacts a convex end surface of the vertical semiconductor channel.
6 . The semiconductor structure of claim 5 , wherein the second end surface segment comprises a convex surface segment located entirely between a first horizontal plane including a first horizontal surface of the source-side spacer layer and a second horizontal plane including a second horizontal surface of the source-side spacer layer.
7 . The semiconductor structure of claim 3 , wherein:
the source-side spacer layer comprises an opening having a tapered conical sidewall; and
the tapered conical sidewall comprises a first tapered conical surface segment that contacts a conical surface segment of the source layer.
8 . The semiconductor structure of claim 7 , wherein a lateral extent of the opening in the source-side spacer layer increases with a vertical distance from a horizontal plane including an interface between the source-side spacer layer and the source layer toward the alternating stack.
9 . The semiconductor structure of claim 7 , wherein the tapered conical sidewall comprises a second tapered conical surface segment that contacts a conical surface segment of an outer sidewall of the memory film.
10 . The semiconductor structure of claim 2 , wherein:
the semiconductor source cap structure further comprises a cylindrical surface segment; and
the first end surface segment is adjoined to a first periphery of the cylindrical surface segment.
11 . The semiconductor structure of claim 10 , further comprising an annular semiconductor ring having an inner cylindrical surface that contacts a first cylindrical area of the cylindrical surface segment of the semiconductor source cap structure.
12 . The semiconductor structure of claim 11 , wherein:
a second cylindrical area of the cylindrical surface segment of the semiconductor source cap structure contacts a cylindrical surface segment of an inner sidewall of the memory film; and
the memory film comprises an annular plate portion that is interposed between the source-side spacer layer and the annular semiconductor ring.
13 . The semiconductor structure of claim 10 , wherein:
the semiconductor source cap structure further comprises second end surface segment that is adjoined to a second periphery of the cylindrical surface segment; and
the second end surface segment comprises a convex surface segment that contacts a concave surface segment of the vertical semiconductor channel.
14 . The semiconductor structure of claim 10 , wherein:
the semiconductor source cap structure has a variable thickness that varies along a radial direction from a vertical axis passing through a geometrical center of the semiconductor source cap structure; and
the semiconductor source cap structure further comprises a central seam that vertically extends from the first end surface segment to a second end surface segment that is adjoined to a second periphery of the cylindrical surface segment.
15 . The semiconductor structure of claim 2 , wherein:
the vertical semiconductor channel has a doping of a first conductivity type;
the source-side spacer layer comprises a semiconductor material layer;
the semiconductor source cap structure comprises a semiconductor material having a doping of a second conductivity type that is an opposite of the first conductivity type;
a first end of the vertical semiconductor channel contacts the semiconductor source cap structure; and
the memory opening fill structure further comprises a drain region having a doping of the second conductivity type and contacting a second end of the vertical semiconductor channel opposite to the first end.
16 . A method of forming a semiconductor structure, comprising:
forming a source-side spacer layer over a carrier substrate;
forming an alternating stack of insulating layers and spacer material layers over the source-side spacer layer, wherein the spacer material layers are formed as or are subsequently replaced with electrically conductive layers;
forming a memory opening through the alternating stack and the source-side spacer layer;
forming a memory film at a peripheral portion of the memory opening;
forming a semiconductor source cap structure at a bottom portion of the memory film;
forming a vertical semiconductor channel on a top surface of the semiconductor source cap structure and on an inner sidewall of the memory film;
removing the carrier substrate; and
forming a source layer on an exposed bottom surface segment of the semiconductor source cap structure.
17 . The method of claim 16 , wherein:
the memory opening comprises a bottom cavity portion having a shape of an inverted cone or an inverted conical frustum; and
the semiconductor source cap structure is formed by conformally depositing and isotropically etching a doped semiconductor material, wherein a remaining portion of the doped semiconductor material comprises the semiconductor source cap structure.
18 . The method of claim 16 , wherein:
the vertical semiconductor channel comprises dopants of a first conductivity type at a first atomic concentration; and
the semiconductor source cap structure comprises dopants of a second conductivity type that is an opposite of the first conductivity type at a second atomic concentration that is higher than the first atomic concentration.
19 . The method of claim 16 , further comprising:
forming a backside stopper layer over the carrier substrate, wherein the source-side spacer layer is formed over the backside stopper layer;
forming an annular recess cavity around the memory opening at a level of the backside stopper layer;
forming an annular semiconductor ring in the annular recess cavity; and
performing a selective semiconductor deposition process that grows a semiconductor material from a physically exposed surface of the annular semiconductor ring, wherein the semiconductor source cap structure comprises a portion of the semiconductor material.
20 . The method of claim 19 , wherein:
the carrier substrate is removed employing a planarization process or an etch process that employs the backside stopper layer as a stopping layer;
the method further comprises removing a physically exposed portion of the memory film and the backside stopper layer; and
the source layer is formed on a bottom surface of the source-side spacer layer and on an exposed cylindrical sidewall of a remaining portion of the memory film after removal of the physically exposed portion of the memory film.