Semiconductor device including distributed write driving arrangement
A semiconductor memory device includes: a local write bit (LWB) line; a local write bit_bar (LWB_bar) line; a global write bit (GWB) line; a global write bit_bar (GWBL_bar) line; a column of segments, each segment including bit cells; each of the bit cells being coupled correspondingly between the LWB and LWB_bar lines; and a distributed write driving arrangement including local write drivers correspondingly coupled to the segments; and a global write driver coupled to each of the local write drivers.
1. A semiconductor memory device comprising:
a local write bit (LWB) line;
a local write bit_bar (LWB_bar) line;
a global write bit (GWB) line;
a global write bit_bar (GWB_bar) line;
a column of segments, each segment including bit cells;
each of the bit cells being coupled correspondingly between the LWB and LWB_bar lines; and
a distributed write driving arrangement including:
local write drivers correspondingly coupled to the segments; and
a global write driver coupled to each of the local write drivers.
2. The semiconductor memory device of claim 1 , wherein:
the local write driver is in a first device layer of the semiconductor device; and
the global write driver is in a second device layer over the first device layer of the semiconductor device.
3. The semiconductor memory device of claim 2 , wherein:
each the local write drivers is at an interior location in the corresponding segment;
the bit cells are in the first device layer;
the LWB line and the LWB_bar line are in a first metallization layer, the first metallization layer being between the first device layer and the second device layer; and
the GWB line and the GWB_bar line are in a second metallization layer, the second metallization layer being between the first metallization layer and the second device layer.
4. The semiconductor memory device of claim 1 , wherein the global write driver includes:
a global equalizer circuit arranged in a switched-coupling between the LWB line and the LWB_bar line, and arranged in a control-coupling with respect to signals correspondingly on the GWB line and the GWB_bar line.
5. The semiconductor memory device of claim 4 , wherein:
the global equalizer circuit includes:
first and second transistors coupled in series between the LWB line and the LWB_bar line; and
gate electrodes of the first and second transistors are coupled correspondingly to the GWB line and the GWB_bar line.
6. The semiconductor memory device of claim 1 , wherein each of the local write drivers includes:
a segment equalizer circuit arranged in a switched-coupling between the LWB line and the LWB_bar line, and arranged in a control-coupling with respect to signals correspondingly on the GWB line and the GWB_bar line.
7. The semiconductor memory device of claim 6 , wherein:
the segment equalizer circuit includes:
first and second transistors coupled in series between the LWB line and the LWB_bar line; and
gate electrodes of the first and second transistors are coupled correspondingly to the GWB line and the GWB_bar line.
8. The semiconductor memory device of claim 1 , wherein:
the global write driver includes a first buffer coupled between the LWB line and the GWB line and a second buffer coupled between the LWB line and the GWB line.
9. The semiconductor memory device of claim 8 , wherein:
the first buffer includes a first inverter and the second buffer includes a second inverter.
10. The semiconductor memory device of claim 1 , wherein:
each of the local write drivers includes a first buffer coupled between the LWB line and the GWB line and a second buffer coupled between the LWB line and the GWB line.
11. The semiconductor memory device of claim 10 , wherein:
the first buffer includes a first inverter and the second buffer includes a second inverter.
12. A semiconductor memory device comprising:
a local write bit (LWB) line;
a local write bit_bar (LWB_bar) line;
a global write bit (GWB) line;
a global write bit_bar (GWB_bar) line;
a column of segments, each segment including bit cells;
each of the bit cells being coupled correspondingly between the LWB and LWB_bar lines; and
a distributed write driving arrangement including:
local write drivers correspondingly coupled such that, for each of the segments, the corresponding local write driver being coupled between the LWB line and the LWB_bar line; and
a global write driver coupled to each of the local write drivers.
13. The semiconductor memory device of claim 12 , wherein:
the local write driver is in a first device layer of the semiconductor device; and
the global write driver is in a second device layer over the first device layer of the semiconductor device.
14. The semiconductor memory device of claim 13 , wherein:
each the local write drivers is at an interior location in the corresponding segment;
the bit cells are in the first device layer;
the LWB line and the LWB_bar line are in a first metallization layer, the first metallization layer being between the first device layer and the second device layer; and
the GWB line and the GWB_bar line are in a second metallization layer, the second metallization layer being between the first metallization layer and the second device layer.
15. The semiconductor memory device of claim 12 , wherein the global write driver includes:
a global equalizer circuit arranged in a switched-coupling between the LWB line and the LWB_bar line, and arranged in a control-coupling with respect to signals correspondingly on the GWB line and the GWB_bar line.
16. The semiconductor memory device of claim 15 , wherein:
the global equalizer circuit includes:
first and second transistors coupled in series between the LWB line and the LWB_bar line; and
gate electrodes of the first and second transistors are coupled correspondingly to the GWB line and the GWB_bar line.
17. A semiconductor memory device comprising:
a local write bit (LWB) line;
a local write bit_bar (LWB_bar) line;
a global write bit (GWB) line;
a global write bit_bar (GWB_bar) line;
a column of segments, each segment including bit cells;
each of the bit cells being coupled correspondingly between the LWB and LWB_bar lines; and
a distributed write driving arrangement including:
local write drivers correspondingly coupled to the segments, each local write driver including a first buffer coupled between the LWB line and the GWB line and a second buffer coupled between the LWB line and the GWB line; and
a global write driver coupled to each of the local write drivers.
18. The semiconductor memory device of claim 17 , wherein:
the first buffer includes a first inverter and the second buffer includes a second inverter.
19. The semiconductor memory device of claim 17 , wherein each of the local write drivers includes:
a segment equalizer circuit arranged in a switched-coupling between the LWB line and the LWB_bar line, and arranged in a control-coupling with respect to signals correspondingly on the GWB line and the GWB_bar line.
20. The semiconductor memory device of claim 19 , wherein:
the segment equalizer circuit includes:
first and second transistors coupled in series between the LWB line and the LWB_bar line; and
gate electrodes of the first and second transistors are coupled correspondingly to the GWB line and the GWB_bar line.