Phase alignment of signals of different frequencies
View Patent ↗A deskew circuit receives a data signal and a clock signal of differing frequencies and indeterminate phase relationship. The deskew circuit selectively applies a delay to a data signal to obtain a delayed data signal. First and second latches of the deskew circuit latch the delayed data signal based on a rising edge and a falling edge of the clock signal, respectively. The deskew circuit detects a phase difference between output signals of the first and second latches. The deskew circuit adjusts the delay applied to the data signal based on the detected phase difference.
1. A method of phase alignment in a circuit, the method comprising:
receiving, by a deskew circuit, a data signal and a clock signal of differing frequencies and indeterminate phase relationship;
selectively applying a delay, by the deskew circuit, to the data signal to obtain a delayed data signal;
latching, by first and second latches of the deskew circuit, the delayed data signal based on a rising edge of the clock signal and based on the falling edge of the clock signal, respectively;
detecting, by the deskew circuit, a phase difference between output signals of the first and second latches; and
adjusting, by the deskew circuit, the delay applied to the data signal based on the detected phase difference.
2. The method of claim 1 , wherein a frequency of the data signal is lower than a frequency of the clock signal.
3. The method of claim 1 , wherein the latching by the first and second latches comprises latching the delayed data signal with first and second D flip-flops.
4. The method of claim 1 , wherein the adjusting comprises aligning a rising edge of the delayed data signal with a falling edge of the clock signal.
5. The method of claim 1 , wherein the adjusting comprises aligning a rising edge of the delayed data signal with a rising edge of the clock signal.
6. The method of claim 1 , wherein the adjusting includes updating a counter within the deskew circuit.
7. An integrated circuit, comprising:
a deskew circuit configured to:
receive a data signal and a clock signal of differing frequencies and indeterminate phase relationship;
selectively apply a delay to the data signal to obtain a delayed data signal;
latch, utilizing first and second latches, the delayed data signal based on a rising edge of the clock signal and based on the falling edge of the clock signal, respectively;
detect a phase difference between output signals of the first and second latches; and
adjust the delay applied to the data signal based on the detected phase difference.
8. The integrated circuit of claim 7 , wherein a frequency of the data signal is lower than a frequency of the clock signal.
9. The integrated circuit of claim 7 , wherein the first and second latches comprise first and second D flip-flops.
10. The integrated circuit of claim 7 , wherein the deskew circuit is configured to align a rising edge of the delayed data signal with a falling edge of the clock signal.
11. The integrated circuit of claim 7 , wherein the deskew circuit is configured to align a rising edge of the delayed data signal with a rising edge of the clock signal.
12. The integrated circuit of claim 7 , wherein the deskew circuit includes a counter having a count value that determines a duration of the delay.
13. An integrated circuit, comprising:
a deskew circuit, including:
a variable delay line configured to selectively apply a delay to a data signal to obtain a delayed data signal based on a delay control signal;
a first latch and a second latch, wherein the first latch is configured to latch the delayed data signal based on a rising edge of the clock signal and the second latch is configured to latch the delayed data signal based on the falling edge of the clock signal;
a delay control circuit coupled to receive output signals of the first and second latches, wherein the delay control circuit includes a phase frequency detector configured to detect a phase difference between output signals of the first and second latches, and wherein the delay control circuit is configured to update the delay control signal, based on the detected phase difference, to adjust the delay applied to the data signal by the variable delay line.
14. The integrated circuit of claim 13 , wherein a frequency of the data signal is lower than a frequency of the clock signal.
15. The integrated circuit of claim 13 , wherein the first and second latches comprise first and second D flip-flops.
16. The integrated circuit of claim 13 , wherein the deskew circuit is configured to align a rising edge of the delayed data signal with a falling edge of the clock signal.
17. The integrated circuit of claim 13 , wherein the deskew circuit is configured to align a rising edge of the delayed data signal with a rising edge of the clock signal.
18. The integrated circuit of claim 7 , wherein:
the deskew circuit includes a counter coupled to the phase frequency detector;
a count value of the counter is updated by the deskew circuit based on the detected phase difference; and
the count value determines the update to the delay control signal.
19. The integrated circuit of claim 7 , further comprising a filter coupled between the phase frequency detector and the counter.