Backplane for an array of emissive elements
A backplane operative to drive an array of emissive pixel elements is disclosed. A plurality of pixel drive circuits form part of an array of emissive elements. The plurality of pixel drive circuits are disposed to form a plurality of rows and a plurality of columns. The plurality of pixel drive circuits are organized into sets of pixel drive circuits, and each set comprises at least one pixel drive circuit.
1 . A pixel drive element comprising:
an output node electrically connected to an emissive element configured to operate based on current supplied by way of the output node;
a selectable current source FET electrically connected between a first bus and the output node and configured to be activated based on a configuration input;
a non-selectable current source FET electrically connected between the first bus and the output node and configured to be activated based on a second bus;
a selectable reference current FET electrically connected between the first bus and a third bus and configured to be activated based on the configuration input;
a non-selectable reference current FET electrically connected between the first bus and the third bus and configured to be activated based on the third bus; and
a switch FET electrically connected between the third bus and the second bus and configured to be activated based on an output of a memory component.
2 . The pixel drive element of claim 1 , wherein:
the configuration input is a first configuration input, the selectable current source FET is a first selectable current source FET, and the selectable reference current FET is a first selectable reference current FET;
the pixel drive element further comprises:
a second selectable current source FET electrically connected between the first bus and the output node and configured to be activated based on a second configuration input, and
a second selectable reference current FET electrically connected between the first bus and the third bus and configured to be activated based on the second configuration input; and
the first configuration input and the second configuration input are operated independently of one another.
3 . The pixel drive element of claim 1 , further comprising a first switch FET, a second switch FET, and an inverter configured to generate an inverse of the configuration input;
wherein the switch FET between the third bus and the second bus is a third switch FET and the selectable reference current FET is configured to be activated based on the configuration input by:
the first switch FET being electrically connected between the first bus and a gate of the selectable reference current FET and having a gate electrically connected to the configuration input, and
the second switch FET being electrically connected between the gate of the selectable reference current FET and the third bus and having a gate electrically connected to the inverse of the configuration input.
4 . The pixel drive element of claim 3 , wherein:
the selectable current source FET is configured to be activated based on the configuration input by having a gate electrically connected to the gate of the selectable reference current FET.
5 . The pixel drive element of claim 1 , further comprising a first switch FET, a second switch FET, and an inverter configured to generate an inverse of the configuration input;
wherein the switch FET between the third bus and the second bus is a third switch FET and the selectable current source FET is configured to be activated based on the configuration input by:
the first switch FET being electrically connected between the first bus and a gate of the selectable current source FET and having a gate electrically connected to the configuration input, and
the second switch FET being electrically connected between the gate of the selectable current source FET and the second bus and having a gate electrically connected to the inverse of the configuration input.
6 . The pixel drive element of claim 5 , further comprising a plurality of additional selectable current source FETs each electrically connected between the first bus and the output node and each configured to be activated based on the configuration input by having a respective gate electrically connected to the gate of the selectable current source FET.
7 . The pixel drive element of claim 1 , further comprising a modulation FET electrically connected between the first bus and the second bus and configured to be activated based on an output of a memory component.
8 . The pixel drive element of claim 1 , further comprising:
a memory component configured to generate an output; and
a bias FET and a bias switch FET serially connected between the third bus and ground, the bias switch FET configured to be activated based on the output of the memory component.
9 . The pixel drive element of claim 8 , wherein:
the output of the memory component is a negative output and the memory component is further configured to generate a positive output that is inverse to the negative output;
the positive output is electrically connected to a gate of a modulation FET electrically connected between the first bus and the second bus; and
the negative output is electrically connected to a gate of the switch FET.
10 . The pixel drive element of claim 9 , further comprising an inverter component electrically connected between the memory component and a gate of the bias switch FET such that the bias switch FET is configured to be activated based on an inverse of the negative output that is separate from the positive output.
11 . The pixel drive element of claim 1 , wherein each of the selectable current source FET, the non-selectable current source FET, the selectable reference current FET, and the non-selectable reference current FET are fabricated to have identical characteristics.
12 . The pixel drive element of claim 1 , wherein the emissive element is a light emitting diode associated with one pixel of an array of pixels.
13 . A display system comprising:
an array of emissive elements arranged in a plurality of rows and a plurality of columns, the array of emissive elements including an emissive element; and
an array of pixel drive elements configured to respectively and independently drive the emissive elements of the array of emissive elements, wherein a pixel drive element of the array of pixel drive elements is configured to drive the emissive element by including:
an output node electrically connected to the emissive element to supply current to the emissive element; and
a reconfigurable current mirror circuit having:
a current source circuit with a selectable current source FET and a non-selectable current source FET, the selectable current source FET being electrically connected between a first bus and the output node and configured to be activated based on a configuration input, the non-selectable current source FET being electrically connected between the first bus and the output node and configured to be activated based on a second bus;
a reference current circuit with selectable reference current FET and a non-selectable reference current FET, the selectable reference current FET being electrically connected between the first bus and a third bus and configured to be activated based on a configuration input, the non-selectable reference current FET being electrically connected between the first bus and the third bus and configured to be activated based on the third bus; and
a switch FET electrically connected between the third bus and the second bus and configured to be activated based on an output of a memory component.
14 . The display system of claim 13 , wherein:
the configuration input is a first configuration input, the selectable current source FET is a first selectable current source FET, and the selectable reference current FET is a first selectable reference current FET;
the current source circuit further includes a second selectable current source FET electrically connected between the first bus and the output node and configured to be activated based on a second configuration input; and
the reference current circuit further includes a second selectable reference current FET electrically connected between the first bus and the third bus and configured to be activated based on the second configuration input.
15 . The display system of claim 14 , wherein the first configuration input and the second configuration input are operated independently of one another.
16 . The display system of claim 14 , wherein the current source circuit includes a modulation FET electrically connected between the first bus and the second bus and configured to be activated based on an output of a memory component.
17 . The display system of claim 14 , wherein the reconfigurable current mirror circuit further includes:
a memory component configured to generate an output; and
a bias FET and a bias switch FET serially connected between the third bus and ground, the bias switch FET configured to be activated based on the output of the memory component.
18 . The display system of claim 14 , wherein each of the first selectable current source FET, the second selectable current source FET, the non-selectable current source FET, the first selectable reference current FET, the second selectable reference current FET, and the non-selectable reference current FET are fabricated to have identical characteristics.