Memory device including semiconductor element
A memory device is formed with at least one memory array, the memory array being formed with a plurality of pages and a plurality of bit lines, each page being formed with a plurality of memory cells arranged in a row direction on a substrate in a plan view, the plurality of memory cells being connected to the bit lines disposed in a column direction. Each of the memory cells included in each of the pages includes a semiconductor base material, a first impurity region and a second impurity region positioned in respective ends of the semiconductor base material, a first gate conductor layer, and a second gate conductor layer. In the memory cell, the first impurity region is connected to a source line, the second impurity region is connected to a bit line, one of the first and second gate conductor layers is connected to a word line, and the other is connected to a plate line. A page erase operation, a page write operation, and a page read operation are performed by controlling a voltage applied to each of the source line, the bit line, the word line, and the plate line. At least one of the bit lines and one of the pages are selected in the page erase operation, the page write operation, and the page read operation, and an erase operation on the memory cell connected to both the bit line and the page thus selected, a write operation of storage data of the sense amplifier circuit to the memory cell, or a read operation from the memory cell to the sense amplifier circuit is executed.
1. A memory device including a semiconductor element, the memory device being formed with at least one memory array, the memory array being formed with a plurality of pages and a plurality of bit lines, each page being formed with a plurality of memory cells arranged in a row direction on a substrate in a plan view, the plurality of memory cells being connected to the bit lines disposed in a column direction, wherein
each of the memory cells included in each of the pages includes:
a semiconductor base material positioned on the substrate and either standing in a vertical direction or extending in a horizontal direction;
a first impurity region and a second impurity region positioned in respective ends of the semiconductor base material;
a gate insulating layer being in contact with a side surface of the semiconductor base material between the first impurity region and the second impurity region;
a first gate conductor layer at least partially covering the gate insulating layer; and
a second gate conductor layer positioned adjacent to the first gate conductor layer and being in contact with the side surface of the gate insulating layer, further wherein
in the memory cell, the first impurity region is connected to a source line, the second impurity region is connected to a corresponding one of the bit lines, one of the first and second gate conductor layers is connected to a word line, and the other is connected to a plate line,
a page erase operation, a page write operation, and a page read operation are performed by controlling a voltage applied to each of the source line, the bit line, the word line, and the plate line,
the bit line is connected to a sense amplifier circuit through a switch circuit, and
at least one of the bit lines and one of the pages are selected in the page erase operation, the page write operation, and the page read operation, and an erase operation on the memory cell connected to both the bit line and the page thus selected, a write operation of storage data of the sense amplifier circuit to the memory cell, or a read operation from the memory cell to the sense amplifier circuit is executed.
2. The memory device including a semiconductor element according to claim 1 , wherein the voltage of the bit line when not selected is set to zero volt or a floating state in the page erase operation, the page write operation, and the page read operation.
3. The memory device including a semiconductor element according to claim 1 , wherein
the voltage applied to each of the source line, the bit line, the word line, and the plate line is controlled to execute, in the page erase operation, an operation that decreases the number of holes remaining in the semiconductor base material by annihilating some holes in the semiconductor base material of the memory cell of the page, and
the voltage applied to each of the source line, the bit line, the word line, and the plate line is controlled to execute, in the page write operation, an operation that increases the number of holes remaining in the semiconductor base material of the selected memory cell of the page through an impact ionization phenomenon.
4. The memory device including a semiconductor element according to claim 1 , wherein
the word line and the plate line are disposed in parallel to each other in a plan view, and
the bit line is disposed in the vertical direction with respect to the word line and the plate line in a plan view.
5. The memory device including a semiconductor element according to claim 1 , wherein a first gate capacitance between the first or second gate conductor layer connected to the plate line and the semiconductor base material is larger than a second gate capacitance between the first or second gate conductor layer connected to the word line and the semiconductor base material.
6. The memory device including a semiconductor element according to claim 1 , wherein the source line is separated for each of the memory cells arranged in the column direction in a plan view and is disposed in parallel to the word line and the plate line.
7. The memory device including a semiconductor element according to claim 1 , wherein the source line is connected in common to all of the memory cells of the pages adjacent to each other in a plan view.
8. The memory device including a semiconductor element according to claim 1 , wherein the semiconductor base material is a P-type semiconductor layer, and the first impurity region and the second impurity region are N-type semiconductor layers.
9. The memory device including a semiconductor element according to claim 1 , wherein in the page erase operation, all of the memory cells connected to at least two pairs of the pages are erased.
10. The memory device including a semiconductor element according to claim 1 , wherein the word line and the plate line are connected to a row decoder circuit, a row address is input to the row decoder circuit, and the page is selected in accordance with the row address.
11. The memory device including a semiconductor element according to claim 1 , wherein the first or second gate conductor layer connected to the plate line is divided in a channel direction into a plurality of parts.
12. The memory device including a semiconductor element according to claim 1 , wherein one or both of the first and second gate conductor layers are divided into two or more separated gate conductor layers in a plan view or in the vertical direction, and the separated gate conductor layers are operated in or out of synchronization.
13. The memory device including a semiconductor element according to claim 12 , wherein the separated gate conductor layers of one of the first and second gate conductor layers are disposed on both sides of the other gate conductor layer in the vertical direction.