Controlling a power consumption of circuitry
An apparatus for managing a power consumption of processor or memory circuitry comprising a plurality of processing or memory functional units may be provided. The processor or memory circuitry is arranged to receive electrical power from an alternating current, AC, power source or a battery. The apparatus comprises processing circuitry to: based on an indication that the processor or memory circuitry is receiving electrical power from the AC power source, selectively cause operational electrical power to be provided to a first number of the functional units of the processor or memory circuitry. The processing circuitry is further to: based on an indication that the circuitry is receiving electrical power from the battery, selectively cause operational electrical power to be provided to a second number of the functional units of the processor or memory circuitry, the second number being less than the first number.
1 . An apparatus comprising:
a processor or memory circuitry; and
processing circuitry coupled to the processor or memory circuitry, the processing circuitry to:
based on an indication that processor or memory circuitry is receiving electrical power from an AC power source, selectively cause operational electrical power to be provided to a first number of a plurality of functional units of the processor or memory circuitry;
based on an indication that the processor or memory circuitry is receiving electrical power from a battery;
selectively cause operational electrical power to be provided to a second number of the plurality of functional units of the processor or memory circuitry, the second number being less than the first number, wherein by the second number being less than the first number, one or both of a static power consumption and an infrastructural power consumption of the processor or memory circuitry is reduced when the processor or memory circuitry is receiving electrical power from the battery, and
improving performance based on using at least part of a power saved by the one or both of the reduced static power consumption and the reduced infrastructural power consumption to provide electrical power to the second number of the plurality of functional units.
2 . The apparatus of claim 1 , wherein the second number of the functional units comprises or consists of a subset of the first number of the functional units.
3 . The apparatus of claim 1 , wherein the processor or memory circuitry comprises a processor, and the plurality of functional units comprises a plurality of processing cores, wherein the processing circuitry of the apparatus is to:
based on the indication that the processor is receiving electrical power from the AC power source, selectively cause operational electrical power to be provided to the first number of the processing cores; and
based on an indication that the processor is receiving electrical power from the battery, selectively cause operational electrical power to be provided to the second number of the processing cores.
4 . The apparatus of claim 3 , wherein the processor comprises any one of: a central processing unit (CPU); a graphics processing unit (GPU); an image processing unit; a digital signal processing unit; and a data processing unit.
5 . The apparatus of claim 3 , wherein the processing cores of the plurality of processing cores are operable to execute instructions in parallel from a common workload.
6 . The apparatus of claim 1 , wherein the processor or memory circuitry comprises a memory circuitry and the plurality of functional units comprises a plurality of memory units, wherein the processing circuitry of the apparatus is to: based on the indication that the memory circuitry is receiving electrical power from the AC power source, selectively cause electrical power to be provided to the first number of the memory units; and based on an indication that the memory circuitry is receiving electrical power from the battery, selectively cause electrical power to be provided to the second number of the memory units.
7 . The apparatus of claim 6 , wherein the memory circuitry is an embedded memory of a discrete graphics processing unit (GPU).
8 . The apparatus of claim 1 , wherein a value of the second number is determined based on an indication of a capacity or a charge state of the battery.
9 . The apparatus of claim 1 , wherein a product of the second number and a clock frequency provided to the second number of functional units is greater than a product of the first number and a maximum clock frequency for the first number of the functional units, the maximum clock frequency for the first number of the functional units being based on a power budget for the processor or memory circuitry when the processor or memory circuitry is receiving electrical power from the battery.
10 . The apparatus of claim 1 , wherein the processing circuitry of the apparatus is to:
based on the indication that the processor or memory circuitry is receiving electrical power from the battery and based on an indication that a charge state of the battery is less than or equal to a predetermined threshold, selectively cause operational electrical power to be provided to a third number of the functional units of the processor or memory circuitry, the third number being less than the second number.
11 . The apparatus of claim 1 , wherein to selectively cause operational electrical power to be provided to the first number of the functional units and to selectively cause operational electrical power to be provided to the second number of the functional units, the processing circuitry of the apparatus is to:
selectively control one or more gates configured to control power delivery to the respective functional units of the processor or memory circuitry.
12 . The apparatus of claim 1 , wherein to selectively cause operational electrical power to be provided to the second number of the functional units, the processing circuitry of the apparatus is to:
disable a provision of a supply voltage to at least a subset of the first number of the functional units; or
disable one or more portions of infrastructural circuitry of the processor or memory circuitry, the one or more portions of the infrastructural circuitry being operably coupled to at least a subset of the first number of the functional units; or
disable provision of a clock signal to at least a subset of the first number of the functional units.
13 . A method comprising:
based on an indication that processor or memory circuitry is receiving electrical power from an AC power source, selectively causing operational electrical power to be provided to a first number of a plurality of functional units of the processor or memory circuitry; and
based on an indication that the processor or memory circuitry is receiving electrical power from a battery;
selectively causing operational electrical power to be provided to a second number of the plurality of functional units of the processor or memory circuitry, the second number being less than the first number, wherein by the second number being less than the first number, one or both of a static power consumption and an infrastructural power consumption of the processor or memory circuitry is reduced when the processor or memory circuitry is receiving electrical power from the battery, and
improving performance based on using at least part of a power saved by the one or both of the reduced static power consumption and the reduced infrastructural power consumption to provide electrical power to the second number of the plurality of functional units.
14 . The method of claim 13 , wherein a value of the second number is determined based on a capacity or a charge state of the battery.
15 . One or more non-transitory computer readable media comprising machine readable instructions which, when executed, perform a method comprising:
based on an indication that processor or memory circuitry is receiving electrical power from an AC power source, selectively causing operational electrical power to be provided to a first number of a plurality of functional units of the processor or memory circuitry; and
based on an indication that the processor or memory circuitry is receiving electrical power from a battery;
selectively causing operational electrical power to be provided to a second number of the plurality of functional units of the processor or memory circuitry, the second number being less than the first number, wherein by the second number being less than the first number, one or both of a static power consumption and an infrastructural power consumption of the processor or memory circuitry is reduced when the processor or memory circuitry is receiving electrical power from the battery, and
improving performance is based on using at least part of a power saved by the one or both of the reduced static power consumption and the reduced infrastructural power consumption to provide electrical power to the second number of the plurality of functional units.
16 . The one or more non-transitory computer readable media of claim 15 , wherein a value of the second number is determined based on an indication of a capacity or a charge state of the battery.