AIR-GAP IN TRENCH FIELD PLATE POWER MOSFET FOR REDUCED POWER LOSS PERFORMANCE
A power MOSFET device including at least one air gap between a buried polysilicon source and a sidewall of a recessed substrate. The device includes a plurality of insulating layers on the substrate and delimiting the air gap.
1 . A device, comprising:
a power MOSFET, including:
a substrate, including:
a recess in a first surface of the substrate, the first surface extending in a first direction, the recess having sidewalls extending in a second direction transverse the first direction, the recess including a second surface extending in the first direction between the sidewalls;
an insulating layer on the first surface of the substrate and in the recess;
a first polysilicon region in the insulating layer, the first polysilicon region extending in the second direction for a first dimension; and
an air gap in the insulating layer between the first polysilicon region and the substrate, the air gap extending in the second direction for a second dimension being less than the first dimension.
2 . The device of claim 1 , wherein the air gap extends in the first direction for a third dimension being less than the second dimension.
3 . The device of claim 1 , wherein the first polysilicon region extends in the first direction for a third dimension being less than the first dimension.
4 . The device of claim 1 , wherein first polysilicon region has a first end spaced from the second surface of the recess for a third dimension.
5 . The device of claim 4 , wherein the air gap has a first end spaced from the second surface of the recess for a fourth dimension, the third dimension being less than the fourth dimension.
6 . The device of claim 1 , comprising a field plate oxide layer in the recess and between the substrate and the insulating layer, the field plate oxide layer having a first surface extending in the first direction adjacent the first surface of the substrate.
7 . The device of claim 6 , wherein the first polysilicon region extends in the field plate oxide layer.
8 . The device of claim 6 , comprising a gate polysilicon region on the first surface of field plate oxide layer, the gate polysilicon region including a protrusion extending into the insulating layer.
9 . The device of claim 8 , comprising a source region and a body region, the source region being on the body region, the body region contacting the first surface of the substrate, a portion of the insulating layer between the gate polysilicon region and the source and body regions.
10 . The device of claim 7 , comprising a nitride layer between the field player oxide layer and the insulating layer, the first polysilicon region extending through the nitride layer.
11 . The device of claim 1 , wherein the air gap is surrounded by the insulating layer.
12 . A device, comprising:
a power MOSFET including:
a recessed substrate;
an insulating layer on the recessed substrate;
a first polysilicon region in the insulating layer;
a first air gap in the insulating layer; and
a second air gap in the insulating layer, the first polysilicon region between the first and second air gaps.
13 . The device of claim 12 , wherein the first and second air gaps are each equally spaced from the first polysilicon region in a first direction.
14 . The device of claim 12 , wherein the first and second air gaps have substantially the same shape and dimensions.
15 . The device of claim 13 , wherein the first and second air gaps extend in a second direction transverse the first direction for a first dimension, the first polysilicon region extends in the second direction for a second dimension greater than the first dimension, the first polysilicon region extending through the insulating layer.
16 . A method, comprising:
forming a power MOSFET device by:
forming a first insulating layer on a substrate including a recess, the first insulating layer covering a first surface of the substrate, recess sidewalls, and a second surface of the recess extending between the sidewalls;
forming a first polysilicon region in the insulating layer; and
forming an air gap in the insulating layer on the substrate.
17 . The method of claim 16 , wherein forming the first polysilicon region includes depositing a first polysilicon material on the first insulating layer and in the recess.
18 . The method of claim 17 , wherein forming the air gap includes etching the insulating layer to expose a surface of the insulating layer that is recessed from the first surface of the substrate.
19 . The method of claim 18 , comprising forming a gate region by depositing a second polysilicon material on the insulating layer and etching the second polysilicon material.
20 . The method of claim 16 , comprising forming source and drain regions on the substrate.