IP Library › Granted Patent US 12,336,096
Granted Patent B1
US 12,336,096 · App. 18/597,541 · Granted Jun 17, 2025

Dielectric, copper clad laminate, circuit board, method for manufacturing copper clad laminate

Inventors: Manami Noda (Osaka, JP); Naozumi Fukushima (Osaka, JP); Takeshi Okunaga (Osaka, JP)
Assignee: NIPPON PILLAR PACKING CO., LTD.
H05K1/036B32B3/00H05K3/022H05K2201/015H05K2201/0209H05K2201/0254
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Quick Facts
Patent No.
US 12,336,096
App. No.
18/597,541
Granted
Jun 17, 2025
Kind
B1
Abstract

To improve electric characteristics of a dielectric for use for a high frequency band. A dielectric 2 formed by lamination of fluorine resin includes a base main layer 3 b containing a base material 3 a and made of melting fluorine resin, a pair of base cover layers 3 c made of melting fluorine resin and formed on both surfaces of the base main layer 3 b , and a pair of functional layers 5 made of fluorine resin mixed with hollow fillers 5 a and laminated on the outer surfaces of the base cover layers 3 c.

Claims (29)

1. A dielectric for a circuit board, which is formed by lamination of fluorine resin, comprising:

a base main layer containing a sheet-shaped base material and made of melting fluorine resin;

a pair of base cover layers made of melting fluorine resin and formed on both surfaces of the base main layer such that at least outer surfaces thereof are positioned apart from the base material; and

a pair of functional layers made of fluorine resin mixed with a hollow filler including a hollow fine particle and laminated on the outer surfaces of the base cover layers, wherein at 10 GHz, a relative permittivity of the dielectric is 2.1 or less, and a dissipation factor of the dielectric is 0.002 or less.

2. The dielectric of claim 1 , wherein

a material of the hollow filler is silica, and a surface thereof is modified, and

at 10 GHz, a relative permittivity of the dielectric is 2.1 or less, and a dissipation factor of the dielectric is 0.002 or less.

3. The dielectric of claim 2 , wherein

the surface of the hollow filler is modified using a silane-based compound.

4. The dielectric of claim 1 , wherein

the base main layer and the base cover layers contain perfluoroalkoxy alkane, and the functional layers contain polytetrafluoroethylene.

5. The dielectric of claim 1 , wherein

a median diameter of the hollow filler is 0.5 μm or more and 20 μm or less.

6. The dielectric of claim 1 , wherein

a volume ratio of the hollow filler with respect to the dielectric is 35% or more and 65% or less.

7. A copper clad laminate comprising:

the dielectric of claim 1 , which includes copper foil as a conductive layer.

8. A circuit board comprising:

the copper clad laminate of claim 7 .

9. A method for manufacturing a copper clad laminate including a dielectric formed by lamination of fluorine resin, comprising:

a step of forming a base main layer by impregnating a base material with melting fluorine resin;

a step of forming a base cover layer by applying melting fluorine resin onto the base main layer;

a step of forming a functional layer by impregnating the base material formed with the base main layer and the base cover layer with fluorine resin mixed with a hollow filler including a hollow fine particle;

a step of acquiring a predetermined molded sheet by cutting prepreg including the base main layer, the base cover layer, and the functional layer into a predetermined size; and

a step of applying copper foil onto a surface of the molded sheet and molding the molded sheet into a plate shape, wherein silica is used as a material of the hollow filler, and treatment of modifying a surface of the hollow filler using a silane-based compound is executed.

10. The manufacturing method of claim 9 , wherein

the silane-based compound to be used includes at least one selected from methyltrimethoxysilane, methyltriethoxysilane, dimethoxydimethylsilane, diethoxydimethylsilane, ethyltrimethoxysilane, ethyltriethoxysilane, propyltrimethoxysilane, propyltriethoxysilane, butyltrimethoxysilane, butyltriethoxysilane, pentyltrimethoxysilane, pentyltriethoxysilane, hexyltrimethoxysilane, hexyltriethoxysilane, octyltrimethoxysilane, octyltriethoxysilane, decyltrimethoxysilane, decyltriethoxysilane, hexamethyldisilazane, trifluoropropyltrimethoxysilane, trifluoropropyltriethoxysilane, diphenyldimethoxysilane, diphenyldiethoxysilane, and diphenylsilanediol.

11. The manufacturing method of claim 9 , wherein

the base main layer and the base cover layer contain perfluoroalkoxy alkane, and the functional layer contains polytetrafluoroethylene.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 8, 2024
From: NODA, MANAMI; FUKUSHIMA, NAOZUMI; OKUNAGA, TAKESHI
To: NIPPON PILLAR PACKING CO., LTD.
Reel/Frame 066703/0821 →
References Cited (11)
US 6417459B1 · Kanzaki · 2002 [cited by examiner]
US 11014336B2 · Okunaga · 2021 [cited by examiner]
US 11529797B2 · Chen · 2022 [cited by examiner]
US 11818838B2 · Chen · 2023 [cited by examiner]
US 20150030824A1 · Crosley · 2015 [cited by applicant]
US 20180339493A1 · Chen · 2018 [cited by examiner]
US 20200404782A1 · Chen · 2020 [cited by examiner]
US 20210060902A1 · Okunaga et al. · 2021 [cited by applicant]
JP H0846309A · 1996 [cited by applicant]
JP 2016534549A1 · 2016 [cited by applicant]
WO 2019049519A1 · 2019 [cited by applicant]