Granted Patent
B2
US 12,720,766 · App. 18/600,957 · Granted Aug 25, 2026
Multi-level memristor elements
View Patent ↗
Loading inventors, assignments & file history…
Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded May 6, 2026
From: CIRRUS LOGIC INTERNATIONAL SEMICONDUCTOR LTD.
To: CIRRUS LOGIC, INC.
Reel/Frame 074582/0345 →
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded Mar 22, 2024
From: LESSO, JOHN P.; DEAS, JAMES T.
To: CIRRUS LOGIC INTERNATIONAL SEMICONDUCTOR LTD.
Reel/Frame 066876/0170 →
Priority Claims (1)
GB 1907685
· May 30, 2019
· national
Continuity (5)
Provisional Application
62801895
· Feb 6, 2019
References Cited (31)
US 3979735A
· Payne
· 1976
[cited by applicant]
US 5585795A
· Yuasa
· 1996
[cited by applicant]
US 6252795B1
· Hansen et al.
· 2001
[cited by applicant]
US 6448815B1
· Talbot
· 2002
[cited by examiner]
US 8773913B1
· Zonte
· 2014
[cited by applicant]
US 20040084710A1
· Baker, Jr.
· 2004
[cited by examiner]
US 20180075904A1
· Ge et al.
· 2018
[cited by applicant]
US 20190244662A1
· Lee
· 2019
[cited by applicant]
CN 107293642A
· 2017
[cited by applicant]
CN 109086249A
· 2018
[cited by applicant]
CN 109217827A
· 2019
[cited by applicant]
CN 109273035A
· 2019
[cited by applicant]
CN 113541691A
· 2021
[cited by examiner]
KR 20170108627A
· 2017
[cited by applicant]
WO 2015163927A1
· 2015
[cited by applicant]
WO 2018051931A1
· 2019
[cited by applicant]
Translation of CN 113541691 A (Year: 2021).
[cited by examiner]
International Search Report and Written Opinion of the International Searching Authority, International Application No. PCT/GB2024/050655, mailed Sep. 27, 2024.
[cited by applicant]
Du, Yuan et al., An Analog Neural Network Computing Enging Using CMOS-Compatible Charge-Trap-Transistor (CTT), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE, USA, vol. 38, No. 10, O…
[cited by applicant]
Combined Search and Examination Report under Sections 17 and 18(3), UKIPO, Application No. GB1907685.0, mailed Sep. 25, 2019.
[cited by applicant]