IP Library › Granted Patent US 12,369,456
Granted Patent B2
US 12,369,456 · App. 18/634,558 · Granted Jul 22, 2025

Pixel circuit having increased capacitance and display device including the same

Inventors: Myeongho Kim (Hwaseong-si, KR); Yeonhong Kim (Hwaseong-si, KR); Jaybum Kim (Yongin-si, KR); Kyoung Seok Son (Seoul, KR); Sunhee Lee (Seoul, KR); Seungjun Lee (Suwon-si, KR); Seunghun Lee (Seoul, KR); Jun Hyung Lim (Seoul, KR)
Assignee: Samsung Display Co., Ltd.
H10K59/1216H10K59/1213H10K71/00H10K59/1201
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,369,456
App. No.
18/634,558
Granted
Jul 22, 2025
Kind
B2
Abstract

A display device includes a first lower electrode disposed on a base substrate, a first upper electrode disposed on the first lower electrode, overlapping the first lower electrode in a plan view, including a silicon semiconductor, and constituting a first capacitor together with the first lower electrode, a second lower electrode disposed on the first upper electrode, and a second upper electrode disposed on the second lower electrode, overlapping the second lower electrode in a plan view, including an oxide semiconductor, and constituting a second capacitor together with the second lower electrode.

Claims (30)

1. A pixel circuit comprising:

a first transistor including a first terminal, a second terminal, and a gate terminal, wherein the gate terminal is connected to a first node;

a second transistor including a first terminal receiving a data voltage, a second terminal connected to the first terminal of the first transistor, and a gate terminal receiving a first gate signal;

a third transistor including a first terminal connected to the second terminal of the first transistor, a second terminal connected to the first node, a gate terminal receiving a second gate signal, and a back-gate terminal receiving the second gate signal;

a first capacitor including a first terminal receiving a high power voltage and a second terminal connected to the first node; and

a second capacitor connected in parallel with the first capacitor between the high power voltage and the first node.

2. The pixel circuit of claim 1 , wherein the first transistor further comprises a back-gate terminal connected to the first node.

3. The pixel circuit of claim 2 , wherein the first transistor and the second transistor are PMOS transistors and the third transistor is an NMOS transistor.

4. A display device comprising:

a light emitting diode connected between a first power voltage line and a second power voltage line which supplies a voltage lower than that of the first power voltage line;

a first transistor serially connected to the light emitting diode between the first power voltage line and the second power voltage line, the first transistor including a first gate electrode, a first active layer which includes a first source electrode and a first drain electrode, and a first back-gate terminal connected to the first gate electrode;

a second transistor connected between the first gate electrode and the first drain electrode of the first transistor, the second transistor including a second gate electrode which receives a gate signal and a second active layer which includes a second source electrode connected to the first drain electrode and a second drain electrode connected to the first gate electrode;

a first capacitor, the first capacitor including a first terminal connected to the first power voltage line and a second terminal connected to the first gate electrode; and

a second capacitor, the second capacitor including a third terminal connected to the first power voltage line and a fourth terminal connected to the first gate electrode,

wherein the first back-gate terminal is disposed on a same layer as the first terminal.

5. The display device of claim 4 , wherein the first active layer and the second terminal are disposed on a same layer and are formed of a same material.

6. The display device of claim 4 , wherein the second transistor further including a second back-gate terminal connected to the second gate electrode and disposed on a same layer as the first gate electrode.

7. The display device of claim 6 , wherein the first terminal and the second terminal do not overlap the second gate electrode in a plan view.

8. The display device of claim 4 , wherein the third terminal and the second active layer are disposed on a same layer and are formed of a same material.

9. The display device of claim 4 , wherein the first terminal and the second terminal overlap the second gate electrode in a plan view.

10. An electronic device, comprising:

a display device; and

a power module that supplies power to the display device,

wherein the display device includes:

a light emitting diode connected between a first power voltage line and a second power voltage line which supplies a voltage lower than that of the first power voltage line;

a first transistor serially connected to the light emitting diode between the first power voltage line and the second power voltage line, the first transistor including a first gate electrode, a first active layer which includes a first source electrode and a first drain electrode, and a first back-gate terminal connected to the first gate electrode;

a second transistor connected between the first gate electrode and the first drain electrode of the first transistor, the second transistor including a second gate electrode which receives a gate signal and a second active layer which includes a second source electrode connected to the first drain electrode and a second drain electrode connected to the first gate electrode;

a first capacitor, the first capacitor including a first terminal connected to the first power voltage line and a second terminal connected to the first gate electrode; and

a second capacitor, the second capacitor including a third terminal connected to the first power voltage line and a fourth terminal connected to the first gate electrode, and

wherein the first back-gate terminal is disposed on a same layer as the first terminal.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 13, 2024
From: KIM, MYEONGHO; KIM, YEONHONG; KIM, JAYBUM; SON, KYOUNG SEOK; LEE, SUNHEE; LEE, SEUNGJUN; LEE, SEUNGHUN; LIM, JUN HYUNG
To: SAMSUNG DISPLAY CO., LTD.
Reel/Frame 067100/0851 →
Priority Claims (1)
KR 10-2020-0166111 · Dec 1, 2020 · national
Continuity (2)
Division 17494892 · Oct 6, 2021
Related Publication 20240260319A1 · Aug 1, 2024
References Cited (15)
US 10490668B2 · Noh et al. · 2019 [cited by applicant]
US 20150236079A1 · Choi · 2015 [cited by applicant]
US 20180062105A1 · Lius et al. · 2018 [cited by applicant]
US 20190006521A1 · Noh et al. · 2019 [cited by applicant]
US 20190148472A1 · Jeon et al. · 2019 [cited by applicant]
US 20190252479A1 · Kang et al. · 2019 [cited by applicant]
US 20190355799A1 · Jeong et al. · 2019 [cited by applicant]
US 20200203393A1 · Hu · 2020 [cited by applicant]
US 20200258970A1 · Park · 2020 [cited by examiner]
KR 1020070072207A · 2007 [cited by applicant]
KR 1020150098281A · 2015 [cited by applicant]
KR 20160013473A · 2016 [cited by examiner]
KR 2018112909A · 2018 [cited by examiner]
TW 538531B · 2003 [cited by applicant]
WO WO2020074998A1 · 2020 [cited by examiner]