IP Library Granted Patent US 12,436,635
Granted Patent B2
US 12,436,635 · App. 18/636,446 · Granted Oct 7, 2025

Semiconductor device including detection electrodes applicable for a touch sensor

Inventors: Mitsuhide Miyamoto (Tokyo, JP); Hajime Akimoto (Tokyo, JP)
Assignee: Magnolia White Corporation
G06F3/0412G06F3/04164G06F3/0446H10K50/11H10K50/17H10K50/171H10K50/8426H10K50/844H10K59/122H10K59/131H10K59/35H10K59/40H10K59/873H10K77/111G06F2203/04102Y02E10/549
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Quick Facts
Patent No.
US 12,436,635
App. No.
18/636,446
Granted
Oct 7, 2025
Kind
B2
Abstract

A sealing member containing conductive particles and disposed in a seal region is formed between a display panel and a touch panel. A laminated structure formed on the display panel includes a first detection lines. The first detection lines extend from the seal region to a connection region and are connected through the conductive particles to terminals of second detection lines formed on the touch panel. A peripheral edge of the organic barrier is located inward from the conductive particles of the sealing member. The above described structure can facilitate a work for connecting external lines such as FPC to the display panel and the touch panel. Further, the structure can secure stability of electrical connection between the external lines and the touch panel.

Claims (59)

1. A semiconductor device comprising:

a substrate including an insulator and a plurality of detection electrodes;

a terminal on the substrate, the terminal located along an edge of the substrate;

a first detection line electrically connected to the terminal; and

a second detection line electrically connected to one of the plurality of detection electrodes, wherein

the insulator overlaps with at least one of the plurality of detection electrodes in a planar view,

the first detection line and the second detection line are electrically connected with each other at a contact portion,

the contact portion is located between the plurality of detection electrodes and an edge of the insulator in the planar view, and

the substrate is configured to be folded back between the contact portion and the terminal.

2. The semiconductor device according to claim 1 , wherein

the insulator comprises multiple layers stacked each other.

3. The semiconductor device according to claim 2 , wherein the multiple layers comprise:

a first inorganic insulating layer;

a second inorganic insulating layer; and

an organic insulating layer between the first inorganic insulating layer and the second inorganic insulating layer, wherein

an edge of the organic insulating layer is located between the plurality of detection electrodes and an edge of the first inorganic insulating layer in the planar view,

the edge of the first inorganic insulating layer is located between the edge of the organic insulating layer and the edge of the substrate in the planar view,

the second inorganic insulating layer is in contact with the first inorganic insulating layer outside the edge of the organic insulating layer, and

the contact portion is located between the edge of the organic insulating layer and the edge of the second inorganic insulating layer in the planar view.

4. The semiconductor device according to claim 3 , wherein

the substrate is configured to be folded back between the edge of the organic insulating layer and the terminal.

5. The semiconductor device according to claim 3 , wherein

the substrate is configured to be folded back between the edge of the first inorganic insulating layer and the terminal.

6. The semiconductor device according to claim 1 , wherein

the terminal is at an opposite side of the plurality of detection electrodes.

7. A semiconductor device comprising:

a substrate including a plurality of detection electrodes;

a terminal on the substrate, the terminal located along an edge of the substrate;

a first detection line electrically connected to the terminal;

a second detection line electrically connected to one of the plurality of detection electrodes; and

a sealing layer between the first detection line and the second detection line, wherein

the first detection line and the second detection line are electrically connected with each other at a contact portion,

the sealing layer overlaps with the contact portion in a planar view, and

the substrate is configured to be folded back between the contact portion and the terminal.

8. The semiconductor device according to claim 7 , wherein

the sealing layer surrounds the plurality of detection electrodes in the planar view.

9. The semiconductor device according to claim 7 , wherein

the substrate is configured to be folded back between the sealing layer and the terminal.

10. The semiconductor device according to claim 7 , wherein

the substrate is configured to be folded back between the edge of the second detection line and the terminal.

11. The semiconductor device according to claim 7 , wherein

the terminal is at an opposite side of the plurality of detection electrodes.

12. A semiconductor device comprising:

a substrate including a plurality of detection electrodes;

a terminal on the substrate, the terminal located along an edge of the substrate;

a first detection line electrically connected to the terminal; and

a second detection line electrically connected to one of the plurality of detection electrodes, wherein

the first detection line and the second detection line are electrically connected with each other at a contact portion,

a sealing layer is provided between the first detection line and the second detection line at the contact portion,

the sealing layer overlaps with the contact portion in a planar view, and

the substrate is configured to be folded back between the contact portion and the terminal.

13. The semiconductor device according to claim 12 , wherein

the sealing layer surrounds the plurality of detection electrodes in the planar view.

14. The semiconductor device according to claim 12 , wherein

the substrate is configured to be folded back between the sealing layer and the terminal.

15. The semiconductor device according to claim 12 , wherein

the substrate is configured to be folded back between the edge of the second detection line and the terminal.

16. The semiconductor device according to claim 12 , wherein

the terminal is at an opposite side of the plurality of detection electrodes.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 29, 2026
From: MARUYAMA, SATOSHI
To: MAGNOLIA WHITE CORPORATION
Reel/Frame 075435/0059 →
CHANGE OF NAME Recorded Jun 26, 2025
From: JAPAN DISPLAY INC.
To: MAGNOLIA WHITE CORPORATION
Reel/Frame 071527/0723 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 16, 2024
From: MIYAMOTO, MITSUHIDE; AKIMOTO, HAJIME
To: JAPAN DISPLAY INC.
Reel/Frame 067117/0690 →
Priority Claims (1)
JP 2016-006329 · Jan 15, 2016 · national
Continuity (8)
Continuation 17862926 · Jul 12, 2022
Continuation 17173610 · Feb 11, 2021
Continuation 16856768 · Apr 23, 2020
Continuation 16453493 · Jun 26, 2019
Continuation 16139844 · Sep 24, 2018
Continuation 15833557 · Dec 6, 2017
Continuation 15336026 · Oct 27, 2016
Related Publication 20240260383A1 · Aug 1, 2024
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