Nonvolatile memory
A nonvolatile memory device includes a plurality of latch groups, an address controller, an encoder, and a buffer. The address controller controls an input address and an output address to indicate one of the plurality of latch groups. The encoder receives sector data from a latch group corresponding to the output address among the plurality of latch groups and also compresses the received sector data. The buffer stores the compressed sector data. Among the plurality of latch groups, the compressed sector data stored in the buffer is overwritten in a latch group corresponding to the input address.
1 . A nonvolatile memory device, comprising:
a plurality of latch groups;
an address controller configured to generate an address control signal, wherein the address control signal includes an input address and an output address, wherein the input address indicates a first latch group of the plurality of latch groups, and wherein the output address indicates a second latch group of the plurality of latch groups;
a compression circuit configured to receive the address control signal from the address controller, to receive sector data from the second latch group corresponding to the output address among the plurality of latch groups and to compress the received sector data; and
a buffer configured to store the compressed sector data,
wherein the compression circuit is configured to overwrite the compressed sector data stored in the buffer in the first latch group among the plurality of latch groups corresponding to the input address.
2 . The nonvolatile memory device of claim 1 , wherein the address controller includes:
a first address controller configured to output the output address under a first address control; and
a second address controller configured to output the input address under a second address control.
3 . The nonvolatile memory device of claim 2 ,
wherein the address controller further includes a multiplexer configured to output either the output address or the input address, and
wherein the first address control and the second address control are the same.
4 . The nonvolatile memory device of claim 3 ,
wherein the first address controller is configured to move, during an output operation, a first address pointer corresponding to the output address from a start point of the sector data to a last point of the sector data, and
wherein the second address controller is configured to move, during an input operation, a second address pointer corresponding to the input address from a start point of the sector data to a point at which a predetermined amount is added to the start point of the sector data.
5 . The nonvolatile memory device of claim 4 , wherein the address controller is configured to retrieve a last point of the first address pointer and a last point of the second address pointer corresponding to a compressing operation for previous sector data during a compressing operation for subsequent sector data.
6 . The nonvolatile memory device of claim 2 ,
wherein the address controller further includes a multiplexer configured to output either the output address or the input address, and
wherein the first address control and the second address control are different.
7 . The nonvolatile memory device of claim 6 ,
wherein the first address controller is configured to move, during an output operation, a first address pointer corresponding to the output address from a start point of the sector data to a last point of the sector data, and
wherein the second address controller is configured to move, during an input operation, a second address pointer corresponding to the input address from a start point of the sector data to a point at which a predetermined amount is added to the start point of the sector data.
8 . The nonvolatile memory device of claim 7 ,
wherein the first address controller is configured to move the first address pointer to a start point corresponding to subsequent sector data during a compressing operation for the subsequent sector data, and
wherein the second address controller is configured to move the second address pointer to a start point corresponding to the subsequent sector data during a compressing operation for the subsequent sector data.
9 . The nonvolatile memory device of claim 1 ,
wherein the sector data is divided into a plurality of data, and
wherein the compression circuit includes a plurality of compression subcircuits configured to compress the plurality of data.
10 . The nonvolatile memory device of claim 9 , wherein the buffer includes a plurality of registers configured to store compressed data from the plurality of compression subcircuits, respectively.
11 . A nonvolatile memory device, comprising:
a plurality of latches;
a plurality of compression circuits configured to compress data of a first size according to a predetermined compression ratio; and
a plurality of registers configured to store the compressed data,
wherein the plurality of latches are configured to output data as large as a first size to the plurality of compression circuits during an output operation while moving a first address pointer, and
wherein the plurality of latches are configured to overwrite compression data of a second size corresponding to the predetermined compression ratio from the plurality of registers while moving a second address pointer during an input operation.
12 . The nonvolatile memory device of claim 11 ,
wherein the first size is 128 bytes, and
wherein the second size is 32 bytes.
13 . The nonvolatile memory device of claim 11 , wherein a first address control corresponding to the output operation and a second address control corresponding to the input operation are the same.
14 . The nonvolatile memory device of claim 11 , wherein a first address control corresponding to the output operation and a second address control corresponding to the input operation are different.
15 . The nonvolatile memory device of claim 11 , wherein compressed data stored in the plurality of latches is output in response to a special command.
16 . A method of operating a nonvolatile memory device, the method comprising:
outputting soft decision data from cache latches under a first address control;
compressing the soft decision data according to a predetermined compression ratio; and
overwriting the compressed soft decision data in a portion of the cache latches under a second address control,
wherein the first address control and the second address control are separated from each other.
17 . The method of claim 16 ,
wherein the cache latches are divided into a plurality of sectors, and
wherein outputting the soft decision data includes outputting the soft decision data from corresponding latches while moving a first address pointer from a start point of a corresponding sector among the plurality of sectors to a last point of the sector under the first address control.
18 . The method of claim 16 , further comprising:
storing the compressed soft decision data in registers.
19 . The method of claim 18 , wherein overwriting a portion of the cache latches includes overwriting data in the registers of a portion of latches while moving a second address pointer by a predetermined amount from a start point of a sector under the second address control.
20 . The method of claim 16 , wherein the first address control and the second address control are the same or different.