Data storage device
A data processing system includes a storage medium, and a controller including a data processing block, configured to receive data from a host, transmit the received data to the storage medium, read data from the storage medium in response to a read request from the host, and decode the read data by the data processing block according to multiple decoding modes. The data processing block includes a first decoder and a second decoder, and is configured to manage the first decoder and the second decoder to run the decoding for the read data, and activate a fast decoding having shorter latency than a normal decoding after a fast decoding condition is satisfied.
1. A memory device comprising:
a transformation unit having a processing unit configured to perform an operation of generating second bit values in parallel, based on first bit values inputted in parallel, the first bit values having relationship to a memory region, and output data consisting of the second bit values; and
an error correcting unit configured to perform an error correcting operation on the data read from the memory region,
wherein the error correcting unit operates without performing normal decoding when a fast decoding condition is satisfied,
and wherein the fast decoding condition is satisfied when an early termination of Low Density Parity Check (LDPC) decoding is activated.
2. The memory device according to claim 1 , wherein the error correcting unit includes a syndrome checker.
3. The memory device according to claim 2 , wherein the syndrome checker outputs decoding information.
4. The memory device according to claim 2 , wherein the syndrome checker checks a syndrome of a codeword in the data.
5. The memory device according to claim 4 , wherein the syndrome represents a checksum of the codeword.
6. The memory device according to claim 4 , wherein the fast decoding condition is satisfied when the syndrome is greater than a checksum threshold.
7. The memory device according to claim 6 , wherein the fast decoding condition is determined after comparing the syndrome and the checksum threshold.
8. The memory device according to claim 1 , wherein the early termination of LDPC decoding is activated according to a result of a decoding on previous data.
9. The memory device according to claim 4 , wherein the early termination is activated after comparing the syndrome and a checksum threshold.
10. The memory device according to claim 1 , wherein, when the early termination is activated, the error correcting unit operates a fast decoding.
11. The memory device according to claim 10 , wherein the error correcting unit changes a decoding mode from the normal decoding to the fast decoding when an inefficient decoding is expected.
12. The memory device according to claim 11 , wherein the inefficient decoding includes a decoding having at least one of long execution time and a decoding ending in failure.
13. The memory device according to claim 10 , wherein the error correcting unit changes a decoding mode from the normal decoding to the fast decoding in response to decoding information stored in a decoding information memory.
14. The memory device according to claim 10 , wherein the error correcting unit changes a decoding mode from the normal decoding to the fast decoding in response to a result of a previous decoding.
15. The memory device according to claim 1 , wherein, when the fast decoding condition is satisfied, the data is transmitted to a memory by bypassing the error correcting unit.
16. The memory device according to claim 15 , wherein, when the fast decoding condition is satisfied, the error correcting unit processes the data in the bypass mode.
17. The memory device according to claim 15 , wherein, when the fast decoding condition is satisfied, the data is transmitted directly to the memory through an input/output circuit without passing the error correcting unit.
18. The memory device according to claim 1 , further including a syndrome checker.
19. The memory device according to claim 18 , wherein the syndrome checker checks a syndrome of a codeword in the data.
20. The memory device according to claim 19 , wherein the syndrome represents a checksum of the codeword.
21. The memory device according to claim 19 , wherein the fast decoding condition is satisfied when the syndrome is greater than a checksum threshold.
22. The memory device according to claim 21 , wherein the fast decoding condition is determined after comparing the syndrome and the checksum threshold.
23. The memory device according to claim 21 , wherein the error correcting unit determines a decoding mode after comparing the syndrome and the checksum threshold.
24. The memory device according to claim 19 , wherein the early termination is activated when the syndrome is greater than a checksum threshold.
25. The memory device according to claim 1 , wherein, when the early termination is activated, the error correcting unit changes a decoding mode from a first decoding mode to a second decoding mode.
26. The memory device according to claim 1 , wherein, when the early termination is activated, the error correcting unit sets a second decoding mode.
27. The memory device according to claim 1 , wherein, when the early termination is activated, the data is retained at a buffer for a time period.
28. The memory device according to claim 27 , wherein the data is transmitted to a second decoder after the time period has elapsed and the second decoder performs an additional decoding for the data.
29. The memory device according to claim 1 , wherein, when the early termination is not activated, the data is transmitted to a first decoder and the first decoder performs the normal decoding for the data.